📄 ptct-send.c
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*
* FUNCTION NAME: InitBDs
*
*
* DESCRIPTION:
*
* Initializes BD rings to point RX BDs to first half of buffer pool and
* TX BDs to second half of buffer pool. This function also initializes the
* buffer descriptors control and data length fields. It also insures that
* transmit and recieve functions are disabled before buffer descriptors
* are initialized.
*
*
* EXTERNAL EFFECTS: Disable Tx/Rx functions. Changes BDs in dual port ram.
*
* PARAMETERS: None
*
* RETURNS: None
*
*-------------------------------------------------------------------------*/
void InitBDs()
{
UHWORD index;
/*-------------------------------------------*/
/* Disable FCC1 while we program the buffer */
/* descriptors and the parameter RAM. */
/* (Just good practice) */
/*-------------------------------------------*/
/*----------------------------------------------------------------*/
/* Clear the ENT/ENR bits in the GFMR -- disable Transmit/Receive */
/*----------------------------------------------------------------*/
(uint32 *)(0xf0000000 +0x11300) &= !(GFMR_ENT | GFMR_ENR);
/*-------------------*/
/* Initialize RxBDs. */
/*-------------------*/
/*-----------------------------------------------------*/
/* Allocate Receive Buffers */
/*-----------------------------------------------------*/
(uint16 *) 0xf0000200 =0xb000;/* Last RX BD. Set the Empty, Wrap, and Interrupt bits */
(uint16 *) 0xf0000202 =0; /* reset */
(uint8 *) 0xf0000204 = NULL;
/*-------------------*/
/* Initialize TxBDs. */
/*-------------------*/
(uint16 *) 0xf0000100 =0xEC00;/* Set Ready, PAD, Wrap, Last, and TC bits */
(uint16 *) 0xf0000102 = BUFFER_SIZE; /* load the buffer length */
(uint16 *) 0xf0000104 = (uint8 *)sendData;/* load the address of the data buffer in external memory */
} /* end InitBDs */
/*--------------------------------------------------------------------------
*
* FUNCTION NAME: InitParallelPorts
*
*
* DESCRIPTION:
*
* Sets up the parallel I/O pins for proper operation of this mode. Uses
* settings generated by the PowerQUICC II PINMUX utility. MII for
* external loopback uses PortC.
*
*
* EXTERNAL EFFECTS: Initializes relevant PIO registers.
*
* PARAMETERS: None
*
* RETURNS: None
*
*-------------------------------------------------------------------------*/
void InitParallelPorts()
{
/* Clear the Port Pin Assignment Registers */
IMM->io_regs[PORTA].ppar = 0x00000000;
IMM->io_regs[PORTB].ppar = 0x00000000;
IMM->io_regs[PORTC].ppar = 0x00000000;
IMM->io_regs[PORTD].ppar = 0x00000000;
/* Clear the Port Data Direction Registers */
IMM->io_regs[PORTA].pdir = 0x00000000;
IMM->io_regs[PORTB].pdir = 0x00000000;
IMM->io_regs[PORTC].pdir = 0x00000000;
IMM->io_regs[PORTD].pdir = 0x00000000;
/* Program the Port Special Options Registers */
IMM->io_regs[PORTA].psor = 0x00000000;
IMM->io_regs[PORTB].psor = 0x00000004;
IMM->io_regs[PORTC].psor = 0x00000000;
IMM->io_regs[PORTD].psor = 0x00000000;
/* Program the Port Data Direction Registers */
IMM->io_regs[PORTA].pdir = 0x00000000;
IMM->io_regs[PORTB].pdir = 0x000003c5;
IMM->io_regs[PORTC].pdir = MDC_PIN_MASK;
IMM->io_regs[PORTD].pdir = 0x00000000;
/* Program the Port Open-Drain Registers */
IMM->io_regs[PORTA].podr = 0x00000000;
IMM->io_regs[PORTB].podr = 0x00000000;
IMM->io_regs[PORTC].podr = 0x00000000;
IMM->io_regs[PORTD].podr = 0x00000000;
/* Program the Port Pin Assignment Registers */
IMM->io_regs[PORTA].ppar = 0x00000000;
IMM->io_regs[PORTB].ppar = 0x00003fff;
IMM->io_regs[PORTC].ppar = 0x00003000;
IMM->io_regs[PORTD].ppar = 0x00000000;
} /* end InitParallelPorts() */
/*------------------------------------------------------------------------
*
* FUNCTION NAME: InterruptControlInit
*
*
* DESCRIPTION:
*
* Initializes interrupt controller for enabling/masking interrupts
*
* EXTERNAL EFFECT:
*
* Interrupts enabled for FCC2, Fast Ethernet
*
* PARAMETERS: None
*
* RETURNS: None
*
*-----------------------------------------------------------------------*/
void InterruptControlInit()
{
/*---------------------------------------------------------------------*/
/* Note that we will be using the default priority config. in the IC */
/*---------------------------------------------------------------------*/
/*-------------------------------------------*/
/* Remove any previous interrupts pending */
/*-------------------------------------------*/
IMM->ic_simr_l = ALL_ZEROS;
/*-------------------------------------------------------*/
/* Enable FCC2 Interrupts to the Interrupt Controller */
/*-------------------------------------------------------*/
IMM->ic_simr_l = SIMR_L_FCC2;
/*------------------------------------------*/
/* Set FCCM for interrupts on TXE, RXF, TXB */
/*------------------------------------------*/
IMM->fcc_regs[FCC2].fccm = 0x001A0000;
/*-----------------------------------------*/
/* Enable External Interrupts at CPU level */
/*-----------------------------------------*/
SetEEinMSR(); /* NOTE: this function uses Diab inline asm syntax */
} /* end InterruptControlInit */
/*------------------------------------------------------------------------
*
* FUNCTION NAME: FCC2Init
*
*
* DESCRIPTION:
*
* FCC2 Fast Ethernet Initialization Routine.
*
* EXTERNAL EFFECT:
*
* Parameter RAM and various registers on the 8260 including interrupt
* related registers and port registers. This function, when complete,
* will initiate or start the transfer of 8 Ethernet frames of data. For
* this simple example, each frame encompasses one BD of data.
*
* PARAMETERS: None
*
* RETURNS: None
*
*-----------------------------------------------------------------------*/
void FCC2Init()
{
uint32 fccIramBace =0xf0008400;
/*初始化有关FCC1相关P口脚，挂接外部时钟*/
sysFccEnetEnable(0xf0000000,1);
/********************************************/
/* Common Parameter RAM Area Initialization */
/********************************************/
MOT_FCC_WORD_WR(fccIramBace+M8260_FCC_RIPTR_OFF) =0x3000;
MOT_FCC_WORD_WR(fccIramBace+M8260_FCC_TIPTR_OFF) =0xb000;
/*------------------------------------------*/
/* Let FCC1 know where base of RxBDs are */
/*------------------------------------------*/
(uint32 *)(fccIramBace + M8260_FCC_RBASE_OFF) = 0xf0000200;;
/*------------------------------------------*/
/* Let FCC1 know where base of TxBDs are */
/*------------------------------------------*/
/*TxBD 设在DPRAM bank3*/
(uint32 *)(fccIramBace + M8260_FCC_TBASE_OFF) = 0xf0000100;
/*-----------------------------------------------------------------*/
/* Set RFCR,TFCR -- Rx,Tx Function Code */
/* */
/* Note that the Function code registers reside in the upper byte */
/* of RSTATE and TSTATE */
/*-----------------------------------------------------------------*/
/* Mot byte ordering, Buffers and BDs on 60x bus */
(uint32 *)(fccIramBace + M8260_FCC_RSTATE_OFF) &= 0x00FFFFFF;
(uint32 *)(fccIramBace + M8260_FCC_RSTATE_OFF) |= 0x10000000;
/* Mot byte ordering, Buffers and BDs on 60x bus */
(uint32 *)(fccIramBace + M8260_FCC_TSTATE_OFF) &= 0x00FFFFFF;
(uint32 *)(fccIramBace + M8260_FCC_TSTATE_OFF) |= 0x10000000;
/*-----------------------------------------------*/
/* Set MRBLR -- Max. Receive Buffer Length */
/* Must be divisible by 32 and not less than 64. */
/*-----------------------------------------------*/
MOT_FCC_WORD_WR(fccIramBace+M8260_FCC_MRBLR_OFF) =ENET_MRBLR;/*288*/
/**************************************************/
/* Ethernet Specific Parameter RAM Initialization */
/**************************************************/
(uint32 *)(fccIramBace + M8260_FCC_C_MASK_OFF) =ENET_C_MASK; /* Constant MASK for CRC */
(uint32 *)(fccIramBace +M8260_FCC_C_PRES_OFF ) =ENET_C_PRES; /* CRC Preset */
(uint32 *)(fccIramBace +M8260_FCC_CRCEC_OFF) =ALL_ZEROS; /* CRC Error Counter */
(uint32 *)(fccIramBace +M8260_FCC_ALEC_OFF) = ALL_ZEROS; /* Align. Error Counter */
(uint32 *)(fccIramBace +M8260_FCC_DISFC_OFF) =ALL_ZEROS; /* Discard Frame Counter */
MOT_FCC_WORD_WR(fccIramBace+M8260_FCC_RET_LIM_OFF) =ENET_RET_LIM; /* Retry Limit Threshold */
MOT_FCC_WORD_WR(fccIramBace+M8260_FCC_P_PER_OFF) = ALL_ZEROS; /* Persistence */
(uint32 *)(fccIramBace +M8260_FCC_GADDR_H_OFF) = ALL_ZEROS; /* Group Addr. Filter 1 */
M8260_FCC_GADDR_L_OFF) = ALL_ZEROS; /* Group Addr. Filter 2 */
MOT_FCC_WORD_WR(fccIramBace+M8260_FCC_TFCSTAT_OFF) =ALL_ZEROS; /* temp BD holder */
MOT_FCC_WORD_WR(fccIramBace+M8260_FCC_MFLR_OFF) = ENET_MFLR; /* Max Frame Length Reg. */
MOT_FCC_WORD_WR(fccIramBace+M8260_FCC_PADDR_H_OFF)= ENET_PADDR_H; /* Phys. Addr. 1 (MSB) */
MOT_FCC_WORD_WR(fccIramBace+M8260_FCC_PADDR_M_OFF)= ENET_PADDR; /* Phys. Addr. 1 */
MOT_FCC_WORD_WR(fccIramBace+M8260_FCC_PADDR_L_OFF)= ENET_PADDR_L; /* Phys. Addr. 1 (LSB) */
(uint32 *)(fccIramBace +M8260_FCC_IADDR_H_OFF)= ALL_ZEROS; /* Ind. Addr. Filter 1 */
(uint32 *)(fccIramBace +M8260_FCC_IADDR_L_OFF)= ALL_ZEROS; /* Ind. Addr. Filter 2 */
(uint32 *)(fccIramBace +M8260_FCC_MINFLR_OFF)= ENET_MINFLR; /* Min Frame Length Reg. */
(uint32 *)(fccIramBace +M8260_FCC_TADDR_H_OFF)= ALL_ZEROS; /* Temp Address (MSB) */
(uint32 *)(fccIramBace +M8260_FCC_TADDR_M_OFF)= ALL_ZEROS; /* Temp Address */
(uint32 *)(fccIramBace +M8260_FCC_TADDR_L_OFF)= ALL_ZEROS; /* Temp Address (LSB) */
(uint32 *)(fccIramBace +M8260_FCC_PAD_PTR_OFF) =0cb000;/* internal pad pointer, can be
same as TIPTR if no specific
character needed. */
(uint32 *)(fccIramBace +M8260_FCC_RES2_OFF)= ALL_ZEROS; /* reserved, cleared */
(uint32 *)(fccIramBace +M8260_FCC_MAXD1_OFF)= ENET_MDMA; /* Max DMA1 Length Reg. */
(uint32 *)(fccIramBace +M8260_FCC_MAXD2_OFF)= ENET_MDMA; /* Max DMA2 Length Reg. */
/****************************/
/* Register Initializations */
/****************************/
/*---------------------------------*/
/* Initialize GFMR: */
/* */
/* MODE = 1100 (ethernet) */
/*---------------------------------*/
(uint32 *) (0xf0000000+ 0x11300) = 0x0000000C;
/* Set DSR to 0xD555 */
/*-------------------*/
(uint16 *) (0xf0000000+ 0x1130c) =ENET_DSR;
/*------------------------------------------------*/
/* Initialize PSMR: */
/* */
/* FDE=1, CRC = 10 (32-bit) */
/*------------------------------------------------*/
(uint32 *) (0xf0000000+ 0x11304) = 0x04000080;
/*-----------------------------------------*/
/* Clear FCCE Register by writing all 1's. */
/*-----------------------------------------*/
/*将FCCE FCCM 合看作一个32位*/
(uint32 *) (0xf0000000+ 0x11310) =0xFFFF0000;
/*-----------------------------------------------------------------*/
/* Issue Init RX & TX Parameters Command for FCC2. This command to */
/* the CR lets it know to reinitialize FCC2 with the new parameter */
/* RAM values. When the ENT/ENR bits are set below, Hunt Mode will */
/* begin automatically. */
/*-----------------------------------------------------------------*/
while((uint32 *)(0xf0000000+ 0x119c0) &CPCR_FLG) != READY_TO_RX_CMD);
(uint32 *)(0xf0000000+ 0x119c0) =CPCR_INIT_TX_RX_PARAMS |
CPCR_FCC1_CH |
CPCR_MCN_FEC |
CPCR_FLG; /* ISSUE COMMAND */
while (((uint32 *)(0xf0000000+ 0x119c0) & CPCR_FLG) != READY_TO_RX_CMD);
/*-------------------------------------------------------------*/
/* Set the ENT/ENR bits in the GFMR -- Enable Transmit/Receive */
/*-------------------------------------------------------------*/
(uint32 *) (0xf0000000+ 0x11300) |= GFMR_ENR | GFMR_ENT;
}/* end FCC2Init() */
/*--------------------------------------------------------------------------
*
* FUNCTION NAME: ExtIntHandler
*
* DESCRIPTION:
*
* Process External Interrupt (assumes only interrupts from FCC2)
*
* Main Processing Steps:
*
* (1) Test input vector against External Interrupt Vector.
*
* (2) Test Interrupt Code in SIU Interrupt Vector Reg (SIVEC) against
* FCC2
*
* (3) Save off FCCE for FCC2 (FCC2 Event Register)
*
* (4) Clear FCC2 Event Register
*
* (5) Process FCC2 event
*
*
* NOTE: This ISR will only handle ONE RX event. This interrupt happens
* when the last frame of eight is received.
*
* EXTERNAL EFFECTS: interrupt related registers
*
* PARAMETERS:
*
* vector - interrupt vector (address)
*
* RETURNS: NONE
*
*-------------------------------------------------------------------------*/
void ExtIntHandler(UWORD vector)
{
UWORD ic_sivec;
UWORD fcce;
UHWORD index = 0;
/*------------------------------------*/
/* Shift the 5-bit interrupt code */
/* down to the least significant bits */
/*------------------------------------*/
ic_sivec = IMM->ic_sivec >> 26; /* sivec interrupt code */
/*-------------------------------------*/
/* Match input vector against External */
/* Interrupt Vector -- 0x500 on PPC */
/*-------------------------------------*/
if (vector != EXT_INT_VECTOR) /* interrupt NOT external to core */
{
while (1)
FlashLed(); /* spin here if error is flagged */
};
/*--------------------------------*/
/* Match event against FCC2 value */
/*--------------------------------*/
if (ic_sivec != SIVEC_FCC2) /* interrupt NOT from FCC 2 */
{
while (1)
FlashLed(); /* spin here if error is flagged */
};
/*-----------------------------*/
/* Copy the FCC event register */
/*-----------------------------*/
fcce = IMM->fcc_regs[FCC2].fcce; /* Save off scce */
/*-------------------------------------------*/
/* Clear FCC2 Event Register (by writing 1s) */
/*-------------------------------------------*/
IMM->fcc_regs[FCC2].fcce = 0xFFFF0000;
/*-------------------------------------------------------------*/
/* Process FCC Ethernet Event if the event flag for RXF is set */
/*-------------------------------------------------------------*/
if (fcce & 0x00080000)
{
/*--------------------------------------------*/
/* Traverse through available Receive Buffers */
/* to locate first filled buffer. */
/*--------------------------------------------*/
while ((!BDEmpty(RxTxBD->RxBD[index].bd_cstatus) &&
(index < NUM_RXBDS)))
{
/*---------------------------------------*/
/* Compare the receive buffer with its */
/* corresponding transmit buffer. */
/*---------------------------------------*/
if (memcmp(&BufferPool[index],
&BufferPool[index+FIRST_TX_BUF],
(BUFFER_SIZE-4)))
{
RxGood=FALSE; /* they didn't compare */
}
/*-----------------------------------------------------------*/
/* In this architecture, every frame encompasses a buffer */
/* descriptor's worth of data. This a very simple example. */
/* Normally there could be several BD's in a frame, and once */
/* a data buffer was processed, it could be released for */
/* use. */
/* */
/* Although not invoked in this example, lines to that */
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