📄 mpc8260.h
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VUWORD si_timers_pitc; /* Periodic Interrupt Count Register */
VUWORD si_timers_pitr; /* Periodic Interrupt Timer Register */
VUBYTE reserved33[0x54]; /* Reserved area */
/* test module registers */
VUWORD tstmhr;
VUWORD tstmlr;
VUHWORD tster;
VUBYTE reserved34[0x156]; /* Reserved area */
/* pci, part 2 */
VUWORD pci_pci; /* PCI Configuration space */
VUBYTE reserved35[0x7fc]; /* Reserved area */
/* ic */
VUHWORD ic_sicr; /* Interrupt Configuration Register */
VUBYTE reserved36[0x2]; /* Reserved area */
VUWORD ic_sivec; /* CP Interrupt Vector Register */
VUWORD ic_sipnr_h; /* Interrupt Pending Register (HIGH) */
VUWORD ic_sipnr_l; /* Interrupt Pending Register (LOW) */
VUWORD ic_siprr; /* SIU Interrupt Priority Register */
VUWORD ic_scprr_h; /* Interrupt Priority Register (HIGH) */
VUWORD ic_scprr_l; /* Interrupt Priority Register (LOW) */
VUWORD ic_simr_h; /* Interrupt Mask Register (HIGH) */
VUWORD ic_simr_l; /* Interrupt Mask Register (LOW) */
VUWORD ic_siexr; /* External Interrupt Control Register */
VUBYTE reserved37[0x58]; /* Reserved area */
/* clocks */
VUWORD clocks_sccr; /* System Clock Control Register */
VUBYTE reserved38[0x4]; /* Reserved area */
VUWORD clocks_scmr; /* System Clock Mode Register */
VUBYTE reserved39[0x4]; /* Reserved area */
VUWORD clocks_rsr; /* Reset Status Register */
VUWORD clocks_rmr; /* Reset Moode Register */
VUBYTE reserved40[0x68]; /* Reserved area */
/* io_ports */
struct io_regs
{
VUWORD pdir; /* Port A-D Data Direction Register */
VUWORD ppar; /* Port A-D Pin Assignment Register */
VUWORD psor; /* Port A-D Special Operation Register */
VUWORD podr; /* Port A-D Open Drain Register */
VUWORD pdat; /* Port A-D Data Register */
VUBYTE reserved41[0xc]; /* Reserved area */
} io_regs[4];
/* cpm_timers */
VUBYTE cpm_timers_tgcr1; /* Timer Global Configuration Register */
VUBYTE reserved42[0x3]; /* Reserved area */
VUBYTE cpm_timers_tgcr2; /* Timer Global Configuration Register */
VUBYTE reserved43[0xb]; /* Reserved area */
VUHWORD cpm_timers_tmr1; /* Timer Mode Register */
VUHWORD cpm_timers_tmr2; /* Timer Mode Register */
VUHWORD cpm_timers_trr1; /* Timer Reference Register */
VUHWORD cpm_timers_trr2; /* Timer Reference Register */
VUHWORD cpm_timers_tcr1; /* Timer Capture Register */
VUHWORD cpm_timers_tcr2; /* Timer Capture Register */
VUHWORD cpm_timers_tcn1; /* Timer Counter */
VUHWORD cpm_timers_tcn2; /* Timer Counter */
VUHWORD cpm_timers_tmr3; /* Timer Mode Register */
VUHWORD cpm_timers_tmr4; /* Timer Mode Register */
VUHWORD cpm_timers_trr3; /* Timer Reference Register */
VUHWORD cpm_timers_trr4; /* Timer Reference Register */
VUHWORD cpm_timers_tcr3; /* Timer Capture Register */
VUHWORD cpm_timers_tcr4; /* Timer Capture Register */
VUHWORD cpm_timers_tcn3; /* Timer Counter */
VUHWORD cpm_timers_tcn4; /* Timer Counter */
VUHWORD cpm_timers_ter[4]; /* Timer Event Register */
VUBYTE reserved44[0x260]; /* Reserved area */
/* sdma general */
VUBYTE sdma_sdsr; /* SDMA Status Register */
VUBYTE reserved45[0x3]; /* Reserved area */
VUBYTE sdma_sdmr; /* SDMA Mask Register */
VUBYTE reserved46[0x3]; /* Reserved area */
/* idma */
VUBYTE idma_idsr1; /* IDMA Status Register */
VUBYTE reserved47[0x3]; /* Reserved area */
VUBYTE idma_idmr1; /* IDMA Mask Register */
VUBYTE reserved48[0x3]; /* Reserved area */
VUBYTE idma_idsr2; /* IDMA Status Register */
VUBYTE reserved49[0x3]; /* Reserved area */
VUBYTE idma_idmr2; /* IDMA Mask Register */
VUBYTE reserved50[0x3]; /* Reserved area */
VUBYTE idma_idsr3; /* IDMA Status Register */
VUBYTE reserved51[0x3]; /* Reserved area */
VUBYTE idma_idmr3; /* IDMA Mask Register */
VUBYTE reserved52[0x3]; /* Reserved area */
VUBYTE idma_idsr4; /* IDMA Status Register */
VUBYTE reserved53[0x3]; /* Reserved area */
VUBYTE idma_idmr4; /* IDMA Mask Register */
VUBYTE reserved54[0x2c3]; /* Reserved area */
/* fcc */
struct fcc_regs
{
VUWORD gfmr; /* FCC General Mode Register */
VUWORD psmr; /* FCC Protocol Specific Mode Register */
VUHWORD todr; /* FCC Transmit On Demand Register */
VUBYTE reserved55[0x2];/* Reserved area */
VUHWORD dsr; /* FCC Data Sync. Register */
VUBYTE reserved56[0x2];/* Reserved area */
VUWORD fcce; /* FCC Event Register */
VUWORD fccm; /* FCC Mask Register */
VUBYTE fccs; /* FCC Status Register */
VUBYTE reserved57[0x3];/* Reserved area */
VUWORD ftprr; /* FCC Transmit Partial Rate Register */
} fcc_regs[3];
VUBYTE reserved58[0x290]; /* Reserved area */
/* brgs 5-8 */
VUWORD brgs_brgc5; /* BRG Configuration Register */
VUWORD brgs_brgc6; /* BRG Configuration Register */
VUWORD brgs_brgc7; /* BRG Configuration Register */
VUWORD brgs_brgc8; /* BRG Configuration Register */
VUBYTE reserved59[0x260]; /* Reserved area */
/* i2c */
VUBYTE i2c_i2mod; /* IC Mode Register */
VUBYTE reserved60[0x3]; /* Reserved area */
VUBYTE i2c_i2add; /* IC Address Register */
VUBYTE reserved61[0x3]; /* Reserved area */
VUBYTE i2c_i2brg; /* IC BRG Register */
VUBYTE reserved62[0x3]; /* Reserved area */
VUBYTE i2c_i2com; /* IC Command Register */
VUBYTE reserved63[0x3]; /* Reserved area */
VUBYTE i2c_i2cer; /* IC Event Register */
VUBYTE reserved64[0x3]; /* Reserved area */
VUBYTE i2c_i2cmr; /* IC Mask Register */
VUBYTE reserved65[0x14b]; /* Reserved area */
/* cpm */
VUWORD cpm_cpcr; /* Communication Processor Command Register */
VUWORD cpm_rccr; /* RISC Configuration Register */
VUWORD cpm_rmdr; /* RISC Microcode Dev. Support Control Reg. */
VUHWORD cpm_rctr1; /* RISC Controller Trap Register */
VUHWORD cpm_rctr2; /* RISC Controller Trap Register */
VUHWORD cpm_rctr3; /* RISC Controller Trap Register */
VUHWORD cpm_rctr4; /* RISC Controller Trap Register */
VUBYTE reserved66[0x2]; /* Reserved area */
VUHWORD cpm_rter; /* RISC Timers Event Register */
VUBYTE reserved67[0x2]; /* Reserved area */
VUHWORD cpm_rtmr; /* RISC Timers Mask Register */
VUHWORD cpm_rtscr; /* RISC Time-Stamp Timer Control Register */
VUHWORD cpm_rmds; /* RISC Development Support Status Register */
VUWORD cpm_rtsr; /* RISC Time-Stamp Register */
VUBYTE reserved68[0xc]; /* Reserved area */
/* brgs 1-4 */
VUWORD brgs_brgc1; /* BRG Configuration Register */
VUWORD brgs_brgc2; /* BRG Configuration Register */
VUWORD brgs_brgc3; /* BRG Configuration Register */
VUWORD brgs_brgc4; /* BRG Configuration Register */
/* scc */
struct scc_regs_8260
{
VUWORD gsmr_l; /* SCC General Mode Register */
VUWORD gsmr_h; /* SCC General Mode Register */
VUHWORD psmr; /* SCC Protocol Specific Mode Register */
VUBYTE reserved69[0x2];/* Reserved area */
VUHWORD todr; /* SCC Transmit-On-Demand Register */
VUHWORD dsr; /* SCC Data Synchronization Register */
VUHWORD scce; /* SCC Event Register */
VUBYTE reserved70[0x2];/* Reserved area */
VUHWORD sccm; /* SCC Mask Register */
VUBYTE reserved71; /* Reserved area */
VUBYTE sccs; /* SCC Status Register */
VUBYTE reserved72[0x8];/* Reserved area */
} scc_regs[4];
/* smc */
struct smc_regs_8260
{
VUBYTE reserved73[0x2];/* Reserved area */
VUHWORD smcmr; /* SMC Mode Register */
VUBYTE reserved74[0x2];/* Reserved area */
VUBYTE smce; /* SMC Event Register */
VUBYTE reserved75[0x3];/* Reserved area */
VUBYTE smcm; /* SMC Mask Register */
VUBYTE reserved76[0x5];/* Reserved area */
} smc_regs[2];
/* spi */
VUHWORD spi_spmode; /* SPI Mode Register */
VUBYTE reserved77[0x4]; /* Reserved area */
VUBYTE spi_spie; /* SPI Event Register */
VUBYTE reserved78[0x3]; /* Reserved area */
VUBYTE spi_spim; /* SPI Mask Register */
VUBYTE reserved79[0x2]; /* Reserved area */
VUBYTE spi_spcom; /* SPI Command Register */
VUBYTE reserved80[0x52]; /* Reserved area */
/* cpm_mux */
VUBYTE cpm_mux_cmxsi1cr; /* CPM MUX SI Clock Route Register */
VUBYTE reserved81; /* Reserved area */
VUBYTE cpm_mux_cmxsi2cr; /* CPM MUX SI Clock Route Register */
VUBYTE reserved82; /* Reserved area */
VUWORD cpm_mux_cmxfcr; /* CPM MUX FCC Clock Route Register */
VUWORD cpm_mux_cmxscr; /* CPM MUX SCC Clock Route Register */
VUBYTE cpm_mux_cmxsmr; /* CPM MUX SMC Clock Route Register */
VUBYTE reserved83; /* Reserved area */
VUHWORD cpm_mux_cmxuar; /* CPM MUX VUTOPIA Address Register */
VUBYTE reserved84[0x10]; /* Reserved area */
/* si */
struct si_regs
{
VUHWORD sixmr[4]; /* SI TDM Mode Registers A-D */
VUBYTE sigmr; /* SI Global Mode Register */
VUBYTE reserved85; /* Reserved area */
VUBYTE sicmdr; /* SI Command Register */
VUBYTE reserved86; /* Reserved area */
VUBYTE sistr; /* SI Status Register */
VUBYTE reserved87; /* Reserved area */
VUHWORD sirsr; /* SI RAM Shadow Address Register */
VUHWORD mcce; /* MCC Event Register */
VUBYTE reserved88[0x2];/* Reserved area */
VUHWORD mccm; /* MCC Mask Register */
VUBYTE reserved89[0x2];/* Reserved area */
VUBYTE mccr; /* MCC Configuration Register */
VUBYTE reserved90[0x7];/* Reserved area */
} si_regs[2];
VUBYTE reserved91[0x4a0]; /* Reserved area */
/* si_ram */
struct si_ram
{
VUHWORD tx_siram[0x100];/* SI Transmit Routing RAM */
VUBYTE reserved92[0x200];/* Reserved area */
VUHWORD rx_siram[0x100];/* SI Receive Routing RAM */
VUBYTE reserved93[0x200];/* Reserved area */
} si_ram[2];
VUBYTE reserved94[0x1000]; /* Reserved area */
} _PackedType t_PQ2IMM;
/***************************************************************************/
/* General Global Definitions */
/***************************************************************************/
#define PORTA 0 /* Index into Parallel I/O Regs Array */
#define PORTB 1 /* Index into Parallel I/O Regs Array */
#define PORTC 2 /* Index into Parallel I/O Regs Array */
#define PORTD 3 /* Index into Parallel I/O Regs Array */
#define PAGE1 0 /* Index 1 into PRAM Array */
#define PAGE2 1 /* Index 2 into PRAM Array */
#define PAGE3 2 /* Index 3 into PRAM Array */
#define PAGE4 3 /* Index 4 into PRAM Array */
#define FCC1 0 /* FCC1 Index into FCC PRAM Array */
#define FCC2 1 /* FCC2 Index into FCC PRAM Array */
#define FCC3 2 /* FCC3 Index into FCC PRAM Array */
#define MCC1 0 /* MCC1 Index into MCC PRAM Array */
#define MCC2 1 /* MCC2 Index into MCC PRAM Array */
#define SCC1 0 /* SCC1 Index into SCC PRAM Array */
#define SCC2 1 /* SCC2 Index into SCC PRAM Array */
#define SCC3 2 /* SCC3 Index into SCC PRAM Array */
#define SCC4 3 /* SCC4 Index into SCC PRAM Array */
#define TDMA 0 /* Index into TDM Mode Register Array */
#define TDMB 1 /* Index into TDM Mode Register Array */
#define TDMC 2 /* Index into TDM Mode Register Array */
#define TDMD 3 /* Index into TDM Mode Register Array */
#endif
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