📄 fenetpq2.c
字号:
for (index = 0; index < NUM_RXBDS; index++)
{
/*--------------------------*/
/* Allocate Receive Buffers */
/*--------------------------*/
RxTxBD->RxBD[index].bd_addr = (UBYTE *)&BufferPool[index];
RxTxBD->RxBD[index].bd_length = 0; /* reset */
if( index != (NUM_RXBDS-1) )
{
RxTxBD->RxBD[index].bd_cstatus = 0x9000; /* Empty */
}
else
{
/*-----------------------------------------------------*/
/* Last RX BD. Set the Empty, Wrap, and Interrupt bits */
/*-----------------------------------------------------*/
RxTxBD->RxBD[index].bd_cstatus = 0xB000;
}
}
/*-------------------*/
/* Initialize TxBDs. */
/*-------------------*/
for (index=0; index < NUM_TXBDS; index++)
{
/*------------------------*/
/* load the buffer length */
/*------------------------*/
RxTxBD->TxBD[index].bd_length = (BUFFER_SIZE-4); // 252 bytes
/*--------------------------------------------------------*/
/* load the address of the data buffer in external memory */
/*--------------------------------------------------------*/
RxTxBD->TxBD[index].bd_addr = (UBYTE *)&BufferPool[FIRST_TX_BUF+index];
if( index != (NUM_TXBDS-1) )
{
/*-------------------------------*/
/* Set Ready, PAD, Last, TC bits */
/*-------------------------------*/
RxTxBD->TxBD[index].bd_cstatus = 0xCC00;
}
else
{
/*-----------------------------------------*/
/* Set Ready, PAD, Wrap, Last, and TC bits */
/*-----------------------------------------*/
RxTxBD->TxBD[index].bd_cstatus = 0xEC00;
}
}
} /* end InitBDs */
/*--------------------------------------------------------------------------
*
* FUNCTION NAME: InitParallelPorts
*
*
* DESCRIPTION:
*
* Sets up the parallel I/O pins for proper operation of this mode. Uses
* settings generated by the PowerQUICC II PINMUX utility. MII for
* external loopback uses PortC.
*
*
* EXTERNAL EFFECTS: Initializes relevant PIO registers.
*
* PARAMETERS: None
*
* RETURNS: None
*
*-------------------------------------------------------------------------*/
void InitParallelPorts()
{
/* Clear the Port Pin Assignment Registers */
IMM->io_regs[PORTA].ppar = 0x00000000;
IMM->io_regs[PORTB].ppar = 0x00000000;
IMM->io_regs[PORTC].ppar = 0x00000000;
IMM->io_regs[PORTD].ppar = 0x00000000;
/* Clear the Port Data Direction Registers */
IMM->io_regs[PORTA].pdir = 0x00000000;
IMM->io_regs[PORTB].pdir = 0x00000000;
IMM->io_regs[PORTC].pdir = 0x00000000;
IMM->io_regs[PORTD].pdir = 0x00000000;
/* Program the Port Special Options Registers */
IMM->io_regs[PORTA].psor = 0x00000000;
IMM->io_regs[PORTB].psor = 0x00000004;
IMM->io_regs[PORTC].psor = 0x00000000;
IMM->io_regs[PORTD].psor = 0x00000000;
/* Program the Port Data Direction Registers */
IMM->io_regs[PORTA].pdir = 0x00000000;
IMM->io_regs[PORTB].pdir = 0x000003c5;
IMM->io_regs[PORTC].pdir = MDC_PIN_MASK;
IMM->io_regs[PORTD].pdir = 0x00000000;
/* Program the Port Open-Drain Registers */
IMM->io_regs[PORTA].podr = 0x00000000;
IMM->io_regs[PORTB].podr = 0x00000000;
IMM->io_regs[PORTC].podr = 0x00000000;
IMM->io_regs[PORTD].podr = 0x00000000;
/* Program the Port Pin Assignment Registers */
IMM->io_regs[PORTA].ppar = 0x00000000;
IMM->io_regs[PORTB].ppar = 0x00003fff;
IMM->io_regs[PORTC].ppar = 0x00003000;
IMM->io_regs[PORTD].ppar = 0x00000000;
} /* end InitParallelPorts() */
/*------------------------------------------------------------------------
*
* FUNCTION NAME: InterruptControlInit
*
*
* DESCRIPTION:
*
* Initializes interrupt controller for enabling/masking interrupts
*
* EXTERNAL EFFECT:
*
* Interrupts enabled for FCC2, Fast Ethernet
*
* PARAMETERS: None
*
* RETURNS: None
*
*-----------------------------------------------------------------------*/
void InterruptControlInit()
{
/*---------------------------------------------------------------------*/
/* Note that we will be using the default priority config. in the IC */
/*---------------------------------------------------------------------*/
/*-------------------------------------------*/
/* Remove any previous interrupts pending */
/*-------------------------------------------*/
IMM->ic_simr_l = ALL_ZEROS;
/*-------------------------------------------------------*/
/* Enable FCC2 Interrupts to the Interrupt Controller */
/*-------------------------------------------------------*/
IMM->ic_simr_l = SIMR_L_FCC2;
/*------------------------------------------*/
/* Set FCCM for interrupts on TXE, RXF, TXB */
/*------------------------------------------*/
IMM->fcc_regs[FCC2].fccm = 0x001A0000;
/*-----------------------------------------*/
/* Enable External Interrupts at CPU level */
/*-----------------------------------------*/
SetEEinMSR(); /* NOTE: this function uses Diab inline asm syntax */
} /* end InterruptControlInit */
/*------------------------------------------------------------------------
*
* FUNCTION NAME: FCC2Init
*
*
* DESCRIPTION:
*
* FCC2 Fast Ethernet Initialization Routine.
*
* EXTERNAL EFFECT:
*
* Parameter RAM and various registers on the 8260 including interrupt
* related registers and port registers. This function, when complete,
* will initiate or start the transfer of 8 Ethernet frames of data. For
* this simple example, each frame encompasses one BD of data.
*
* PARAMETERS: None
*
* RETURNS: None
*
*-----------------------------------------------------------------------*/
void FCC2Init()
{
t_EnetFcc_Pram* FCC2Ethernet;
/*--------------------------------------------*/
/* Connect FCC2's Tx and Rx clocks to BRG5 */
/* if in internal loopback mode. */
/*--------------------------------------------*/
if (loopback == INTERNAL)
{
IMM->cpm_mux_cmxfcr = ALL_ZEROS;
IMM->cpm_mux_cmxuar = ALL_ZEROS;
IMM->clocks_sccr &= 0xFFFFFFFC;
IMM->brgs_brgc5 = 0x00010006;
}
/*--------------------------------------------*/
/* If in external loopback mode connect */
/* FCC2's Tx to CLK14 and Rx clocks to CLK13 */
/*--------------------------------------------*/
else
{
IMM->cpm_mux_cmxuar = ALL_ZEROS;
IMM->cpm_mux_cmxfcr = 0x00250000;
};
/********************************************/
/* Common Parameter RAM Area Initialization */
/********************************************/
IMM->pram.serials.fcc_pram[FCC2].riptr = 0x3000;
IMM->pram.serials.fcc_pram[FCC2].tiptr = 0xb000;
/*------------------------------------------*/
/* Let FCC2 know where base of RxBDs are */
/*------------------------------------------*/
IMM->pram.serials.fcc_pram[FCC2].rbase = (UWORD)&RxTxBD->RxBD[0];
/*------------------------------------------*/
/* Let FCC2 know where base of TxBDs are */
/*------------------------------------------*/
IMM->pram.serials.fcc_pram[FCC2].tbase = (UWORD)&RxTxBD->TxBD[0];
/*-----------------------------------------------------------------*/
/* Set RFCR,TFCR -- Rx,Tx Function Code */
/* */
/* Note that the Function code registers reside in the upper byte */
/* of RSTATE and TSTATE */
/*-----------------------------------------------------------------*/
/* Mot byte ordering, Buffers and BDs on 60x bus */
IMM->pram.serials.fcc_pram[FCC2].rstate &= 0x00FFFFFF;
IMM->pram.serials.fcc_pram[FCC2].rstate |= 0x10000000;
/* Mot byte ordering, Buffers and BDs on 60x bus */
IMM->pram.serials.fcc_pram[FCC2].tstate &= 0x00FFFFFF;
IMM->pram.serials.fcc_pram[FCC2].tstate |= 0x10000000;
/*-----------------------------------------------*/
/* Set MRBLR -- Max. Receive Buffer Length */
/* Must be divisible by 32 and not less than 64. */
/*-----------------------------------------------*/
IMM->pram.serials.fcc_pram[FCC2].mrblr = ENET_MRBLR;
/**************************************************/
/* Ethernet Specific Parameter RAM Initialization */
/**************************************************/
/* set up abbreviated pointer */
FCC2Ethernet =
(t_EnetFcc_Pram * ) &(IMM->pram.serials.fcc_pram[FCC2].SpecificProtocol.e);
FCC2Ethernet->c_mask = ENET_C_MASK; /* Constant MASK for CRC */
FCC2Ethernet->c_pres = ENET_C_PRES; /* CRC Preset */
FCC2Ethernet->crcec = ALL_ZEROS; /* CRC Error Counter */
FCC2Ethernet->alec = ALL_ZEROS; /* Align. Error Counter */
FCC2Ethernet->disfc = ALL_ZEROS; /* Discard Frame Counter */
FCC2Ethernet->ret_lim = ENET_RET_LIM; /* Retry Limit Threshold */
FCC2Ethernet->p_per = ALL_ZEROS; /* Persistence */
FCC2Ethernet->gaddr_h = ALL_ZEROS; /* Group Addr. Filter 1 */
FCC2Ethernet->gaddr_l = ALL_ZEROS; /* Group Addr. Filter 2 */
FCC2Ethernet->tfcstat = ALL_ZEROS; /* temp BD holder */
FCC2Ethernet->mflr = ENET_MFLR; /* Max Frame Length Reg. */
FCC2Ethernet->paddr1_h = ENET_PADDR_H; /* Phys. Addr. 1 (MSB) */
FCC2Ethernet->paddr1_m = ENET_PADDR; /* Phys. Addr. 1 */
FCC2Ethernet->paddr1_l = ENET_PADDR_L; /* Phys. Addr. 1 (LSB) */
FCC2Ethernet->iaddr_h = ALL_ZEROS; /* Ind. Addr. Filter 1 */
FCC2Ethernet->iaddr_l = ALL_ZEROS; /* Ind. Addr. Filter 2 */
FCC2Ethernet->minflr = ENET_MINFLR; /* Min Frame Length Reg. */
FCC2Ethernet->taddr_h = ALL_ZEROS; /* Temp Address (MSB) */
FCC2Ethernet->taddr_m = ALL_ZEROS; /* Temp Address */
FCC2Ethernet->taddr_l = ALL_ZEROS; /* Temp Address (LSB) */
FCC2Ethernet->pad_ptr =
IMM->pram.serials.fcc_pram[FCC2].tiptr;/* internal pad pointer, can be
same as TIPTR if no specific
character needed. */
FCC2Ethernet->cf_type = ALL_ZEROS; /* reserved, cleared */
FCC2Ethernet->maxd1 = ENET_MDMA; /* Max DMA1 Length Reg. */
FCC2Ethernet->maxd2 = ENET_MDMA; /* Max DMA2 Length Reg. */
/****************************/
/* Register Initializations */
/****************************/
/*---------------------------------*/
/* Initialize GFMR: */
/* */
/* MODE = 1100 (ethernet) */
/*---------------------------------*/
IMM->fcc_regs[FCC2].gfmr = 0x0000000C;
if (loopback == INTERNAL)
IMM->fcc_regs[FCC2].gfmr |= 0x60000000; /* DIAG=01 (Local Loopback Mode), TCI = 1 */
/*-------------------*/
/* Set DSR to 0xD555 */
/*-------------------*/
IMM->fcc_regs[FCC2].dsr = ENET_DSR;
/*------------------------------------------------*/
/* Initialize PSMR: */
/* */
/* LPB=1, FDE=1, CRC = 10 (32-bit) */
/*------------------------------------------------*/
IMM->fcc_regs[FCC2].psmr = 0x14000080;
/*-----------------------------------------*/
/* Clear FCCE Register by writing all 1's. */
/*-----------------------------------------*/
IMM->fcc_regs[FCC2].fcce = 0xFFFF0000;
/*-----------------------------------------------------------------*/
/* Issue Init RX & TX Parameters Command for FCC2. This command to */
/* the CR lets it know to reinitialize FCC2 with the new parameter */
/* RAM values. When the ENT/ENR bits are set below, Hunt Mode will */
/* begin automatically. */
/*-----------------------------------------------------------------*/
while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD);
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
CPCR_FCC2_CH |
CPCR_MCN_FEC |
CPCR_FLG; /* ISSUE COMMAND */
while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD);
/*-------------------------------------------------------------*/
/* Set the ENT/ENR bits in the GFMR -- Enable Transmit/Receive */
/*-------------------------------------------------------------*/
IMM->fcc_regs[FCC2].gfmr |= GFMR_ENR | GFMR_ENT;
}/* end FCC2Init() */
/*--------------------------------------------------------------------------
*
* FUNCTION NAME: ExtIntHandler
*
* DESCRIPTION:
*
* Process External Interrupt (assumes only interrupts from FCC2)
*
* Main Processing Steps:
*
* (1) Test input vector against External Interrupt Vector.
*
* (2) Test Interrupt Code in SIU Interrupt Vector Reg (SIVEC) against
* FCC2
*
* (3) Save off FCCE for FCC2 (FCC2 Event Register)
*
* (4) Clear FCC2 Event Register
*
* (5) Process FCC2 event
*
*
* NOTE: This ISR will only handle ONE RX event. This interrupt happens
* when the last frame of eight is received.
*
* EXTERNAL EFFECTS: interrupt related registers
*
* PARAMETERS:
*
* vector - interrupt vector (address)
*
* RETURNS: NONE
*
*-------------------------------------------------------------------------*/
void ExtIntHandler(UWORD vector)
{
UWORD ic_sivec;
UWORD fcce;
UHWORD index = 0;
/*------------------------------------*/
/* Shift the 5-bit interrupt code */
/* down to the least significant bits */
/*------------------------------------*/
ic_sivec = IMM->ic_sivec >> 26; /* sivec interrupt code */
/*-------------------------------------*/
/* Match input vector against External */
/* Interrupt Vector -- 0x500 on PPC */
/*-------------------------------------*/
if (vector != EXT_INT_VECTOR) /* interrupt NOT external to core */
{
while (1)
FlashLed(); /* spin here if error is flagged */
};
/*--------------------------------*/
/* Match event against FCC2 value */
/*--------------------------------*/
if (ic_sivec != SIVEC_FCC2) /* interrupt NOT from FCC 2 */
{
while (1)
FlashLed(); /* spin here if error is flagged */
};
/*-----------------------------*/
/* Copy the FCC event register */
/*-----------------------------*/
fcce = IMM->fcc_regs[FCC2].fcce; /* Save off scce */
/*-------------------------------------------*/
/* Clear FCC2 Event Register (by writing 1s) */
/*-------------------------------------------*/
IMM->fcc_regs[FCC2].fcce = 0xFFFF0000;
/*-------------------------------------------------------------*/
/* Process FCC Ethernet Event if the event flag for RXF is set */
/*-------------------------------------------------------------*/
if (fcce & 0x00080000)
{
/*--------------------------------------------*/
/* Traverse through available Receive Buffers */
/* to locate first filled buffer. */
/*--------------------------------------------*/
while ((!BDEmpty(RxTxBD->RxBD[index].bd_cstatus) &&
(index < NUM_RXBDS)))
{
/*---------------------------------------*/
/* Compare the receive buffer with its */
/* corresponding transmit buffer. */
/*---------------------------------------*/
if (memcmp(&BufferPool[index],
&BufferPool[index+FIRST_TX_BUF],
(BUFFER_SIZE-4)))
{
RxGood=FALSE; /* they didn't compare */
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -