fenetpq2.c

mpc8260 fcc ethernet code

/*--------------------------------------------------------------------------                
*
* FILE: fcc2tr.c
*
* DESCRIPTION: 
*
*  Exercises FCC2 Ethernet transmit/receive functions, using RX interrupts. 
*  This program allows the user to choose between internal and external 
*  loopback in order to send 8 Ethernet frames, with each frame containing a 
*  different data pattern. FCC2 will receive all 8 frames and then vector 
*  to the external interrupt. In this interrupt, all 8 Rx frames will be 
*  checked against it's corresponding Tx frame. It also checks for Rx 
*  errors. If any errors or mismatches exist then the red GP1 LED on the 
*  MPC8260ADS board will be flashed. If the transfer of data was 
*  successful the green GP0 LED will stay lit constantly.
*
*  For a high level explanation, please refer to the applications document
*  for this example. This is included in the Zip file you received. If you 
*  are interested in a MPC8260ADS development/evaluation system, please 
*  contact your local sales representative.
*              
*
* NOTES  <<<IMPORTANT:  PLEASE READ>>>:
*
*     1) Specifically Designed to run on MPC8260ADS board.
*
*     2) Make sure that data and BDs are either in global (snooped) areas
*        of memory or that cache is disabled for that area.
*
*     3) Using internal loopback mode, the driver tests the transmitted
*        information against the received and turns on the green GP0
*        LED on the ADS board if there is an exact match. If there is
*        not a match, then the red GP1 LED will light.  
*
*     4) This driver also takes an external interrupt on a full ethernet
*        packet reception.  If an unanticipated external interrupt
*        occurs (non FCC2), the red GP1 LED will flash.
*
*
* REFERENCES: 
*
*      1) MPC8260 Users Manual
*      2) MPC603e Users manual
*      3) PowerPC Microprocessor Family: The Programming Environments for 
*         32-Bit Microprocessors
*
* HISTORY:
*
* 15 SEP 1998   ggh     initial version
*
* 24 NOV 1999   jms     Modified code for PILOT Rev boards.  The code now reads
*                       BCSR2 for the board revision and then chooses the correct
*                       bit positionings for BCSR0 and BCSR1.   
*
* 13 AUG 2002   ddc     Modified code to include external loopback option using
*						the Lxt970 Transceiver
*  
*-------------------------------------------------------------------------*/

#include <string.h>
#include <stdlib.h>        
#include "netcomm.h"       /* global defines */
#include "mpc8260.h"       /* IMM definitions and declarations */
#include "ethernet.h"      /* Local header file */

/***********************/
/* Global Declarations */
/***********************/

t_PQ2IMM  *IMM;           /* Internal Memory Map base pointer */
BDRINGS *RxTxBD;          /* buffer descriptors base pointer */
UWORD Revision;           /* Specifies eng vs pilot rev of ADS board */ 
t_BCSR *CSR;			  /* Board Control & Status Reg pointer */

UHWORD loopback;          /* Specifies which loopback mode is to be used */

/*----------------------------------------------------------*/
/* Set of Data Buffers for Transparent Receive and Transmit */
/* Data. The Rx buffer pools will take up the first 8       */
/* buffers and the Tx buffer pools will take up the last 8. */
/*----------------------------------------------------------*/

LB BufferPool[NUM_RXBDS+NUM_TXBDS];

/*---------------------------------------------------------*/
/* Status parameters of the receive and transmit processes */
/*---------------------------------------------------------*/

VUBYTE  NotDone;        /* Termination of Rx flag */
VUBYTE  RxProcIndex;    /* keeps track of next BD to process */
VUWORD  RxGood;         /* Successful RX flag */

/*-----------------------------------------------------*/
/* Interrupt Handler Code to be moved to Address 0x500 */
/*-----------------------------------------------------*/

extern UWORD ExtIntTable[];

/***********************/
/* Function Prototypes */
/***********************/
                       
void     Main(void);
void     InterruptVectorInit(UWORD *, UWORD[]);
void     LoadTxBuffers(void);
void     InitBDs(void);
void     InitParallelPorts(void);
void     InterruptControlInit(void);
void     FCC2Init(void);
void     ExtIntHandler(UWORD);
UHWORD   BDRxError(UHWORD);
UHWORD   BDEmpty(UHWORD);
UHWORD   LastBD(UHWORD);
void     Led(UHWORD);
void     FlashLed(void);
void     SetEEinMSR(void);
int		 InitLxt970Transceiver(void);
UWORD	 MdioReceive(int);
void 	 MdioSend(UWORD,int);
int		 MdioFrame(int,int,int,int);



/*--------------------------------------------------------------------------
*
* FUNCTION NAME:  main 
*
* DESCRIPTION:
*
*  Main function for MPC8260 Fast Ethernet example code.
*
* EXTERNAL EFFECT: 
*                 
* PARAMETERS:  None
*
* RETURNS: None
*
*-------------------------------------------------------------------------*/

void Main()

{
int wait;
int trans_error;

	/*--------------------------------------------------*/
	/* Initialize loopback mode as INTERNAL or EXTERNAL */
	/*--------------------------------------------------*/

	loopback=EXTERNAL;

    /*------------------------*/
    /* Establish IMM pointer  */
    /*------------------------*/
   
    IMM = (t_PQ2IMM *)(BASE_ADDR);  /* pointer to MPC8260 internal memory map. */

    
    /* Getting the board revision, eng or pilot */

    CSR = (t_BCSR *)(IMM->memc_regs[1].br & 0xFFFF8000);
    Revision = CSR->bcsr2;
    Revision = (Revision & 0x00000F00) >> 8;  
    
	CSR->bcsr1 &= ~0x0c000000;      // active low FETHIEN on BSCR1, assert reset low
  	CSR->bcsr1 |=  0x04000000;      // de-assert reset
   
    /*------------------------------------------*/
    /* Additional flag and board initialization */
    /*------------------------------------------*/

    NotDone = TRUE;     /* initialize as not done */
    RxProcIndex = 0;    /* initialize */
    RxGood = TRUE;      /* initialize as good */
    Led(OFF);           /* turn off signal LEDs */
  

    /*--------------------------------------------------------*/
    /* Place External Interrupt Handler Code to Address 0x500 */
    /*--------------------------------------------------------*/

    InterruptVectorInit((UWORD *) EXT_INT_VECTOR, ExtIntTable);

    /*---------------------------------------------------------*/
    /* Establish base pointer for Tx and Rx buffer descriptors */
    /*---------------------------------------------------------*/

    RxTxBD = (BDRINGS *)(BDRING_BASE);    
    
    /*------------------------------------------------*/
    /* Load the Tx buffer pool with the test patterns */
    /*------------------------------------------------*/

    LoadTxBuffers();

    /*-------------------------------------------------------------------*/
    /* This function defines a number of buffers for an RX and TX buffer */
    /* pool, but does not attempt to manage memory.  It uses the first   */
    /*  half of the BD pool for RX and the second half for TX.           */ 
    /*-------------------------------------------------------------------*/
   
    InitBDs();    /* Initialize RX and TX BDs for ethernet */

    /*----------------------------------*/
    /* Initialize the parallel I/O pins */
    /*----------------------------------*/
   
    InitParallelPorts();

    
	/*-----------------------------------*/
	/* Initialize Lxt970 transceiver if  */
	/* in external loopback mode 	     */
	/*-----------------------------------*/

	if (loopback == EXTERNAL)
	{
		trans_error = InitLxt970Transceiver();

		if (trans_error == -1)  
			FlashLed();	  /* if transceiver is not writing data */
						  /* correctly red LED will flash */
				
		/* Allow transceiver time to initialize */

	    for (wait=0; wait < 1000000; wait++){};
	}

    /*----------------------------------------------------------------*/
    /* Initialize the Interrupt Controller to properly enable or mask */
    /* interrupts                                                     */
    /*----------------------------------------------------------------*/
   
    InterruptControlInit();
       

    /*-----------------------------------------------------------*/
    /* Initialize and enable FCC2 in Ethernet                    */
    /*-----------------------------------------------------------*/

    FCC2Init();    /* Note that this routine also enables Tx and Rx */


    /*------------------------------------------------------------------*/
    /* If there were any errors, the ETH LED will flash. This action is */
    /* initiated in the interrupt handler where the checking takes      */
    /* place.  Once reception is complete, and no errors were found,    */
    /* the ETH LED will come on and stay constantly lit.                */
    /*------------------------------------------------------------------*/

    while (1)
    {
        /*-------------------------------------------------------*/
        /* Stay in this tight loop if the transfer of data was   */
        /* successful. If there wasn't success, the code stays   */
        /* loop in the external interrupt handler.               */
        /*-------------------------------------------------------*/

        /*-------------------------------------------------------*/
        /* Turn On Ethernet LED to indicate error-free reception */
        /*-------------------------------------------------------*/

	    Led(GREEN);
    }

}  /* End Main */

/*--------------------------------------------------------------------------
*
* FUNCTION NAME: InterruptVectorInit
*
*
* DESCRIPTION:
*
*     Copy Interrupt Handler code from its current address to the 
*     specified PowerPC Interrupt Vector.
*
* EXTERNAL EFFECTS:
*
* PARAMETERS:  
*
*     interrupt_vector -- address to which interrupt code should be copied
*     interrupt_code   -- current address of interrupt code
*
* RETURNS: NONE
*
*--------------------------------------------------------------------------*/

void InterruptVectorInit(UWORD *interrupt_vector,
                   UWORD interrupt_code[])

{

UHWORD index;
UWORD *instruction;
UWORD *next_vector;


   next_vector = (interrupt_vector + VECTOR_BLOCK_LEN); /* next vector entry */

   for(instruction = interrupt_vector, index = 0; instruction < next_vector;
       instruction++, index++)
      
      *instruction = interrupt_code[index];

} /* end InterruptInit */

/*-------------------------------------------------------------------------
*
* FUNCTION NAME:  LoadTxBuffers
*
*           
* DESCRIPTION:
*
*  This function loads all 8 Tx buffers with Ethernet header 
*  information, followed by the following data patterns:
*
*     Buffer 0: 0x55
*     Buffer 1: 0xAA
*     Buffer 2: 0x00
*     Buffer 3: 0xFF
*     Buffer 4: Increasing Walking Ones
*     Buffer 5: Decreasing Walking Ones
*     Buffer 6: Increment from 0
*     Buffer 7: Decrement from 255
*
*   The Tx buffers are initialized as shown:
*
*                   |             |              |
*        DEST ADDR  | SOURCE ADDR |  TYPE\LENGTH |     DATA
*        (6 bytes)  |  (6 bytes)  |   (2 bytes)  | (238 bytes)
*
*  This results in a total of 252 bytes. Ethernet's 32-bit CRC is 
*  transmitted after the last data byte, so the Rx buffers receive 
*  252 + 4 = 256 bytes.                                                  
*
* EXTERNAL EFFECTS:
*
*  BufferPool loaded
*
* PARAMETERS: none
*
*  RETURNS: none
*
*-------------------------------------------------------------------------*/

void  LoadTxBuffers()

{

UHWORD   index, pattern, bufcount;

   /*---------------------------------------------------*/
   /* Load buffers 0 through 3 with the following data  */
   /* patterns:                                         */
   /*                                                   */
   /* Buffer[0] = 0x55                                  */
   /* Buffer[1] = 0xAA                                  */
   /* Buffer[2] = 0x00                                  */
   /* Buffer[3] = 0xFF                                  */
   /*---------------------------------------------------*/
    
   for (index = 12; index < (BUFFER_SIZE-4); index++)

   {
      BufferPool[FIRST_TX_BUF][index]   = 0x55;
      BufferPool[FIRST_TX_BUF+1][index] = 0xAA;
      BufferPool[FIRST_TX_BUF+2][index] = 0x00;
      BufferPool[FIRST_TX_BUF+3][index] = 0xFF;      
   }     
 

   /*-----------------------------------------*/
   /* Buffer[4]: Load increasing walking ones */
   /*-----------------------------------------*/
 
  
   for (index = 12,pattern = 1; index < (BUFFER_SIZE-4); index++,pattern<<=1)

   {
      if (pattern == 0x0100)

         pattern = 0x01;

      BufferPool[FIRST_TX_BUF+4][index] = pattern;     
   }


   /*-----------------------------------------*/
   /* Buffer[5]: Load decreasing walking ones */
   /*-----------------------------------------*/
  
   
   for (index = 12,pattern = 0x80; index < (BUFFER_SIZE-4); index++,pattern>>=1)

   {
      if (pattern == 0x00)

         pattern = 0x80;

      BufferPool[FIRST_TX_BUF+5][index] = pattern;
   }

 
   /*--------------------------------------------*/
   /* Buffer[6]: Load "Increment from 0" pattern */
   /*--------------------------------------------*/


   for (index = 12; index < (BUFFER_SIZE-4); index++)

   {
      BufferPool[FIRST_TX_BUF+6][index] = index-2;
   }

   
   /*----------------------------------------------*/
   /* Buffer[7]: Load "Decrement from 255" pattern */
   /*----------------------------------------------*/

     
   for (index = 12; index < (BUFFER_SIZE-4); index++)

   {
      BufferPool[FIRST_TX_BUF+7][index] = (257-index);
   }


   /*-----------------------------------------------*/
   /* Load destination addresses, source addresses, */
   /* and type/length field into each Tx buffer     */
   /*-----------------------------------------------*/

   
        bufcount = 0;

        while (bufcount < 8)
        {
                BufferPool[FIRST_TX_BUF + bufcount][0]  = 0x00;
                BufferPool[FIRST_TX_BUF + bufcount][6]  = 0x00;
                BufferPool[FIRST_TX_BUF + bufcount][1]  = 0x19;
                BufferPool[FIRST_TX_BUF + bufcount][7]  = 0x19;
                BufferPool[FIRST_TX_BUF + bufcount][2]  = 0x22;
                BufferPool[FIRST_TX_BUF + bufcount][8]  = 0x22;
                BufferPool[FIRST_TX_BUF + bufcount][3]  = 0x33;
                BufferPool[FIRST_TX_BUF + bufcount][9]  = 0x33;
                BufferPool[FIRST_TX_BUF + bufcount][4]  = 0x48;
                BufferPool[FIRST_TX_BUF + bufcount][10] = 0x48; 
                BufferPool[FIRST_TX_BUF + bufcount][5]  = 0x55;
                BufferPool[FIRST_TX_BUF + bufcount][11] = 0x55;
                BufferPool[FIRST_TX_BUF + bufcount][12] = 0x00;
                BufferPool[FIRST_TX_BUF + bufcount][13] = 0xEE;
         
         bufcount++;
         
        }
                            
} /* end of LoadTxBuffers */


/*--------------------------------------------------------------------------
*
* FUNCTION NAME:  InitBDs
*
*
* DESCRIPTION:
*
*  Initializes BD rings to point RX BDs to first half of buffer pool and 
*  TX BDs to second half of buffer pool. This function also initializes the 
*  buffer descriptors control and data length fields. It also insures that 
*  transmit and recieve functions are disabled before buffer descriptors 
*  are initialized.
*
*   
* EXTERNAL EFFECTS: Disable Tx/Rx functions. Changes BDs in dual port ram.
*
* PARAMETERS: None
*
* RETURNS: None
*
*-------------------------------------------------------------------------*/

void InitBDs()

{
UHWORD index;

   /*-------------------------------------------*/
   /* Disable FCC2 while we program the buffer  */
   /* descriptors and the parameter RAM.        */
   /* (Just good practice)                      */
   /*-------------------------------------------*/

   /*----------------------------------------------------------------*/
   /* Clear the ENT/ENR bits in the GFMR -- disable Transmit/Receive */
   /*----------------------------------------------------------------*/

    IMM->fcc_regs[FCC2].gfmr &= !(GFMR_ENT | GFMR_ENR);

   /*-------------------*/
   /* Initialize RxBDs. */
   /*-------------------*/