📄 newport.h
字号:
unsigned int lsmode; unsigned int lspattern; unsigned int lspatsave; unsigned int zpattern; unsigned int colorback; unsigned int colorvram; unsigned int alpharef; unsigned int smask0x; unsigned int smask0y; unsigned int _xstart; unsigned int _ystart; unsigned int _xend; unsigned int _yend; unsigned int xsave; unsigned int xymove; unsigned int bresd; unsigned int bress1; unsigned int bresoctinc1; unsigned int bresrndinc2; unsigned int brese1; unsigned int bress2; unsigned int aweight0; unsigned int aweight1; unsigned int colorred; unsigned int coloralpha; unsigned int colorgrn; unsigned int colorblue; unsigned int slopered; unsigned int slopealpha; unsigned int slopegrn; unsigned int slopeblue; unsigned int wrmask; unsigned int hostrw0; unsigned int hostrw1; /* configregs */ unsigned int smask1x; unsigned int smask1y; unsigned int smask2x; unsigned int smask2y; unsigned int smask3x; unsigned int smask3y; unsigned int smask4x; unsigned int smask4y; unsigned int topscan; unsigned int xywin; unsigned int clipmode; unsigned int config; /* dcb registers */ unsigned int dcbmode; unsigned int dcbdata0; unsigned int dcbdata1;} newport_ctx;/* Reading/writing VC2 registers. */#define VC2_REGADDR_INDEX 0x00000000#define VC2_REGADDR_IREG 0x00000010#define VC2_REGADDR_RAM 0x00000030#define VC2_PROTOCOL (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000)#define VC2_VLINET_ADDR 0x000#define VC2_VFRAMET_ADDR 0x400#define VC2_CGLYPH_ADDR 0x500/* Now the Indexed registers of the VC2. */#define VC2_IREG_VENTRY 0x00#define VC2_IREG_CENTRY 0x01#define VC2_IREG_CURSX 0x02#define VC2_IREG_CURSY 0x03#define VC2_IREG_CCURSX 0x04#define VC2_IREG_DENTRY 0x05#define VC2_IREG_SLEN 0x06#define VC2_IREG_RADDR 0x07#define VC2_IREG_VFPTR 0x08#define VC2_IREG_VLSPTR 0x09#define VC2_IREG_VLIR 0x0a#define VC2_IREG_VLCTR 0x0b#define VC2_IREG_CTPTR 0x0c#define VC2_IREG_WCURSY 0x0d#define VC2_IREG_DFPTR 0x0e#define VC2_IREG_DLTPTR 0x0f#define VC2_IREG_CONTROL 0x10#define VC2_IREG_CONFIG 0x20extern __inline__ void newport_vc2_set(struct newport_regs *regs, unsigned char vc2ireg, unsigned short val){ regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 | NPORT_DMODE_ECINC | VC2_PROTOCOL); regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8);}extern __inline__ unsigned short newport_vc2_get(struct newport_regs *regs, unsigned char vc2ireg){ regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 | NPORT_DMODE_ECINC | VC2_PROTOCOL); regs->set.dcbdata0.bybytes.b3 = vc2ireg; regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 | NPORT_DMODE_ECINC | VC2_PROTOCOL); return regs->set.dcbdata0.byshort.s1;}/* VC2 Control register bits */#define VC2_CTRL_EVIRQ 0x0001#define VC2_CTRL_EDISP 0x0002#define VC2_CTRL_EVIDEO 0x0004#define VC2_CTRL_EDIDS 0x0008#define VC2_CTRL_ECURS 0x0010#define VC2_CTRL_EGSYNC 0x0020#define VC2_CTRL_EILACE 0x0040#define VC2_CTRL_ECDISP 0x0080#define VC2_CTRL_ECCURS 0x0100#define VC2_CTRL_ECG64 0x0200#define VC2_CTRL_GLSEL 0x0400/* Controlling the color map on NEWPORT. */#define NCMAP_REGADDR_AREG 0x00000000#define NCMAP_REGADDR_ALO 0x00000000#define NCMAP_REGADDR_AHI 0x00000010#define NCMAP_REGADDR_PBUF 0x00000020#define NCMAP_REGADDR_CREG 0x00000030#define NCMAP_REGADDR_SREG 0x00000040#define NCMAP_REGADDR_RREG 0x00000060#define NCMAP_PROTOCOL (0x00008000 | 0x00040000 | 0x00800000)static __inline__ void newport_cmap_setaddr(struct newport_regs *regs, unsigned short addr){ regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL | NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC | NCMAP_REGADDR_AREG | NPORT_DMODE_W2); regs->set.dcbdata0.byshort.s1 = addr; regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL | NCMAP_REGADDR_PBUF | NPORT_DMODE_W3);}static __inline__ void newport_cmap_setrgb(struct newport_regs *regs, unsigned char red, unsigned char green, unsigned char blue){ regs->set.dcbdata0.byword = (red << 24) | (green << 16) | (blue << 8);}/* Miscellaneous NEWPORT routines. */#define BUSY_TIMEOUT 100000static __inline__ int newport_wait(void){ int i = 0; while(i < BUSY_TIMEOUT) if(!(npregs->cset.status & NPORT_STAT_GBUSY)) break; if(i == BUSY_TIMEOUT) return 1; return 0;}static __inline__ int newport_bfwait(void){ int i = 0; while(i < BUSY_TIMEOUT) if(!(npregs->cset.status & NPORT_STAT_BBUSY)) break; if(i == BUSY_TIMEOUT) return 1; return 0;}/* newport.c and cons_newport.c routines */extern struct graphics_ops *newport_probe (int, const char **);void newport_save (void *);void newport_restore (void *);void newport_reset (void);int newport_ioctl (int card, int cmd, unsigned long arg);/* * DCBMODE register defines: *//* Width of the data being transferred for each DCBDATA[01] word */#define DCB_DATAWIDTH_4 0x0#define DCB_DATAWIDTH_1 0x1#define DCB_DATAWIDTH_2 0x2#define DCB_DATAWIDTH_3 0x3/* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */#define DCB_ENDATAPACK (1 << 2)/* Enables DCBCRS auto increment after each DCB transfer */#define DCB_ENCRSINC (1 << 3)/* shift for accessing the control register select address (DBCCRS, 3 bits) */#define DCB_CRS_SHIFT 4/* DCBADDR (4 bits): display bus slave address */#define DCB_ADDR_SHIFT 7#define DCB_VC2 (0 << DCB_ADDR_SHIFT)#define DCB_CMAP_ALL (1 << DCB_ADDR_SHIFT)#define DCB_CMAP0 (2 << DCB_ADDR_SHIFT)#define DCB_CMAP1 (3 << DCB_ADDR_SHIFT)#define DCB_XMAP_ALL (4 << DCB_ADDR_SHIFT)#define DCB_XMAP0 (5 << DCB_ADDR_SHIFT)#define DCB_XMAP1 (6 << DCB_ADDR_SHIFT)#define DCB_BT445 (7 << DCB_ADDR_SHIFT)#define DCB_VCC1 (8 << DCB_ADDR_SHIFT)#define DCB_VAB1 (9 << DCB_ADDR_SHIFT)#define DCB_LG3_BDVERS0 (10 << DCB_ADDR_SHIFT)#define DCB_LG3_ICS1562 (11 << DCB_ADDR_SHIFT)#define DCB_RESERVED (15 << DCB_ADDR_SHIFT)/* DCB protocol ack types */#define DCB_ENSYNCACK (1 << 11)#define DCB_ENASYNCACK (1 << 12)#define DCB_CSWIDTH_SHIFT 13#define DCB_CSHOLD_SHIFT 18#define DCB_CSSETUP_SHIFT 23/* XMAP9 specific defines *//* XMAP9 -- registers as seen on the DCBMODE register*/# define XM9_CRS_CONFIG (0 << DCB_CRS_SHIFT)# define XM9_PUPMODE (1 << 0)# define XM9_ODD_PIXEL (1 << 1)# define XM9_8_BITPLANES (1 << 2)# define XM9_SLOW_DCB (1 << 3)# define XM9_VIDEO_RGBMAP_MASK (3 << 4)# define XM9_EXPRESS_VIDEO (1 << 6)# define XM9_VIDEO_OPTION (1 << 7)# define XM9_CRS_REVISION (1 << DCB_CRS_SHIFT)# define XM9_CRS_FIFO_AVAIL (2 << DCB_CRS_SHIFT)# define XM9_FIFO_0_AVAIL 0# define XM9_FIFO_1_AVAIL 1# define XM9_FIFO_2_AVAIL 3# define XM9_FIFO_3_AVAIL 2# define XM9_FIFO_FULL XM9_FIFO_0_AVAIL# define XM9_FIFO_EMPTY XM9_FIFO_3_AVAIL# define XM9_CRS_CURS_CMAP_MSB (3 << DCB_CRS_SHIFT)# define XM9_CRS_PUP_CMAP_MSB (4 << DCB_CRS_SHIFT)# define XM9_CRS_MODE_REG_DATA (5 << DCB_CRS_SHIFT)# define XM9_CRS_MODE_REG_INDEX (7 << DCB_CRS_SHIFT)#define DCB_CYCLES(setup,hold,width) \ ((hold << DCB_CSHOLD_SHIFT) | \ (setup << DCB_CSSETUP_SHIFT)| \ (width << DCB_CSWIDTH_SHIFT))#define W_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 0)#define WSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (5, 5, 0)#define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0)#define R_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 3)static __inline__ voidxmap9FIFOWait (struct newport_regs *rex){ rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL | DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL; newport_bfwait (); while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY) ;}static __inline__ voidxmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq){ if (cfreq > 119) rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL; else if (cfreq > 59) rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL; else rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL; rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff);}#define BT445_PROTOCOL DCB_CYCLES(1,1,3)#define BT445_CSR_ADDR_REG (0 << DCB_CRS_SHIFT)#define BT445_CSR_REVISION (2 << DCB_CRS_SHIFT)#define BT445_REVISION_REG 0x01#endif /* !(_SGI_NEWPORT_H) */⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -