sungem.h

linux和2410结合开发 用他可以生成2410所需的zImage文件

#define PCS_MIISTAT_RF	0x00000010	/* Remote Fault			*/
#define PCS_MIISTAT_ANC	0x00000020	/* Auto-neg complete		*/
#define PCS_MIISTAT_ES	0x00000100	/* Extended Status, always 1	*/

/* PCS MII Advertisement Register. */
#define PCS_MIIADV_FD	0x00000020	/* Advertise Full Duplex	*/
#define PCS_MIIADV_HD	0x00000040	/* Advertise Half Duplex	*/
#define PCS_MIIADV_SP	0x00000080	/* Advertise Symmetric Pause	*/
#define PCS_MIIADV_AP	0x00000100	/* Advertise Asymmetric Pause	*/
#define PCS_MIIADV_RF	0x00003000	/* Remote Fault			*/
#define PCS_MIIADV_ACK	0x00004000	/* Read-only			*/
#define PCS_MIIADV_NP	0x00008000	/* Next-page, forced low	*/

/* PCS MII Link Partner Ability Register.   This register is equivalent
 * to the Link Partnet Ability Register of the standard MII register set.
 * It's layout corresponds to the PCS MII Advertisement Register.
 */

/* PCS Configuration Register. */
#define PCS_CFG_ENABLE	0x00000001	/* Must be zero while changing
					 * PCS MII advertisement reg.
					 */
#define PCS_CFG_SDO	0x00000002	/* Signal detect override	*/
#define PCS_CFG_SDL	0x00000004	/* Signal detect active low	*/
#define PCS_CFG_JS	0x00000018	/* Jitter-study:
					 * 0 = normal operation
					 * 1 = high-frequency test pattern
					 * 2 = low-frequency test pattern
					 * 3 = reserved
					 */
#define PCS_CFG_TO	0x00000020	/* 10ms auto-neg timer override	*/

/* PCS Interrupt Status Register.  This register is self-clearing
 * when read.
 */
#define PCS_ISTAT_LSC	0x00000004	/* Link Status Change		*/

/* Datapath Mode Register. */
#define PCS_DMODE_SM	0x00000001	/* 1 = use internal Serialink	*/
#define PCS_DMODE_ESM	0x00000002	/* External SERDES mode		*/
#define PCS_DMODE_MGM	0x00000004	/* MII/GMII mode		*/
#define PCS_DMODE_GMOE	0x00000008	/* GMII Output Enable		*/

/* Serialink Control Register.
 *
 * NOTE: When in SERDES mode, the loopback bit has inverse logic.
 */
#define PCS_SCTRL_LOOP	0x00000001	/* Loopback enable		*/
#define PCS_SCTRL_ESCD	0x00000002	/* Enable sync char detection	*/
#define PCS_SCTRL_LOCK	0x00000004	/* Lock to reference clock	*/
#define PCS_SCTRL_EMP	0x00000018	/* Output driver emphasis	*/
#define PCS_SCTRL_STEST	0x000001c0	/* Self test patterns		*/
#define PCS_SCTRL_PDWN	0x00000200	/* Software power-down		*/
#define PCS_SCTRL_RXZ	0x00000c00	/* PLL input to Serialink	*/
#define PCS_SCTRL_RXP	0x00003000	/* PLL input to Serialink	*/
#define PCS_SCTRL_TXZ	0x0000c000	/* PLL input to Serialink	*/
#define PCS_SCTRL_TXP	0x00030000	/* PLL input to Serialink	*/

/* Shared Output Select Register.  For test and debug, allows multiplexing
 * test outputs into the PROM address pins.  Set to zero for normal
 * operation.
 */
#define PCS_SOS_PADDR	0x00000003	/* PROM Address			*/

/* PROM Image Space */
#define PROM_START	0x100000UL	/* Expansion ROM run time access*/
#define PROM_SIZE	0x0fffffUL	/* Size of ROM			*/
#define PROM_END	0x200000UL	/* End of ROM			*/

/* MII definitions missing from mii.h */

#define BMCR_SPD2	0x0040		/* Gigabit enable? (bcm5411)	*/
#define LPA_PAUSE	0x0400

/* More PHY registers (specific to Broadcom models) */

/* MII BCM5201 MULTIPHY interrupt register */
#define MII_BCM5201_INTERRUPT			0x1A
#define MII_BCM5201_INTERRUPT_INTENABLE		0x4000

#define MII_BCM5201_AUXMODE2			0x1B
#define MII_BCM5201_AUXMODE2_LOWPOWER		0x0008

#define MII_BCM5201_MULTIPHY                    0x1E

/* MII BCM5201 MULTIPHY register bits */
#define MII_BCM5201_MULTIPHY_SERIALMODE         0x0002
#define MII_BCM5201_MULTIPHY_SUPERISOLATE       0x0008

/* MII BCM5400 1000-BASET Control register */
#define MII_BCM5400_GB_CONTROL			0x09
#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP	0x0200

/* MII BCM5400 AUXCONTROL register */
#define MII_BCM5400_AUXCONTROL                  0x18
#define MII_BCM5400_AUXCONTROL_PWR10BASET       0x0004

/* MII BCM5400 AUXSTATUS register */
#define MII_BCM5400_AUXSTATUS                   0x19
#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK     0x0700
#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT    8  

/* When it can, GEM internally caches 4 aligned TX descriptors
 * at a time, so that it can use full cacheline DMA reads.
 *
 * Note that unlike HME, there is no ownership bit in the descriptor
 * control word.  The same functionality is obtained via the TX-Kick
 * and TX-Complete registers.  As a result, GEM need not write back
 * updated values to the TX descriptor ring, it only performs reads.
 *
 * Since TX descriptors are never modified by GEM, the driver can
 * use the buffer DMA address as a place to keep track of allocated
 * DMA mappings for a transmitted packet.
 */
struct gem_txd {
	u64	control_word;
	u64	buffer;
};

#define TXDCTRL_BUFSZ	0x0000000000007fff	/* Buffer Size		*/
#define TXDCTRL_CSTART	0x00000000001f8000	/* CSUM Start Offset	*/
#define TXDCTRL_COFF	0x000000001fe00000	/* CSUM Stuff Offset	*/
#define TXDCTRL_CENAB	0x0000000020000000	/* CSUM Enable		*/
#define TXDCTRL_EOF	0x0000000040000000	/* End of Frame		*/
#define TXDCTRL_SOF	0x0000000080000000	/* Start of Frame	*/
#define TXDCTRL_INTME	0x0000000100000000	/* "Interrupt Me"	*/
#define TXDCTRL_NOCRC	0x0000000200000000	/* No CRC Present	*/

/* GEM requires that RX descriptors are provided four at a time,
 * aligned.  Also, the RX ring may not wrap around.  This means that
 * there will be at least 4 unused desciptor entries in the middle
 * of the RX ring at all times.
 *
 * Similar to HME, GEM assumes that it can write garbage bytes before
 * the beginning of the buffer and right after the end in order to DMA
 * whole cachelines.
 *
 * Unlike for TX, GEM does update the status word in the RX descriptors
 * when packets arrive.  Therefore an ownership bit does exist in the
 * RX descriptors.  It is advisory, GEM clears it but does not check
 * it in any way.  So when buffers are posted to the RX ring (via the
 * RX Kick register) by the driver it must make sure the buffers are
 * truly ready and that the ownership bits are set properly.
 *
 * Even though GEM modifies the RX descriptors, it guarentees that the
 * buffer DMA address field will stay the same when it performs these
 * updates.  Therefore it can be used to keep track of DMA mappings
 * by the host driver just as in the TX descriptor case above.
 */
struct gem_rxd {
	u64	status_word;
	u64	buffer;
};

#define RXDCTRL_TCPCSUM	0x000000000000ffff	/* TCP Pseudo-CSUM	*/
#define RXDCTRL_BUFSZ	0x000000007fff0000	/* Buffer Size		*/
#define RXDCTRL_OWN	0x0000000080000000	/* GEM owns this entry	*/
#define RXDCTRL_HASHVAL	0x0ffff00000000000	/* Hash Value		*/
#define RXDCTRL_HPASS	0x1000000000000000	/* Passed Hash Filter	*/
#define RXDCTRL_ALTMAC	0x2000000000000000	/* Matched ALT MAC	*/
#define RXDCTRL_BAD	0x4000000000000000	/* Frame has bad CRC	*/

#define RXDCTRL_FRESH(gp)	\
	((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \
	 RXDCTRL_OWN)

#define TX_RING_SIZE 128
#define RX_RING_SIZE 128

#if TX_RING_SIZE == 32
#define TXDMA_CFG_BASE	TXDMA_CFG_RINGSZ_32
#elif TX_RING_SIZE == 64
#define TXDMA_CFG_BASE	TXDMA_CFG_RINGSZ_64
#elif TX_RING_SIZE == 128
#define TXDMA_CFG_BASE	TXDMA_CFG_RINGSZ_128
#elif TX_RING_SIZE == 256
#define TXDMA_CFG_BASE	TXDMA_CFG_RINGSZ_256
#elif TX_RING_SIZE == 512
#define TXDMA_CFG_BASE	TXDMA_CFG_RINGSZ_512
#elif TX_RING_SIZE == 1024
#define TXDMA_CFG_BASE	TXDMA_CFG_RINGSZ_1K
#elif TX_RING_SIZE == 2048
#define TXDMA_CFG_BASE	TXDMA_CFG_RINGSZ_2K
#elif TX_RING_SIZE == 4096
#define TXDMA_CFG_BASE	TXDMA_CFG_RINGSZ_4K
#elif TX_RING_SIZE == 8192
#define TXDMA_CFG_BASE	TXDMA_CFG_RINGSZ_8K
#else
#error TX_RING_SIZE value is illegal...
#endif

#if RX_RING_SIZE == 32
#define RXDMA_CFG_BASE	RXDMA_CFG_RINGSZ_32
#elif RX_RING_SIZE == 64
#define RXDMA_CFG_BASE	RXDMA_CFG_RINGSZ_64
#elif RX_RING_SIZE == 128
#define RXDMA_CFG_BASE	RXDMA_CFG_RINGSZ_128
#elif RX_RING_SIZE == 256
#define RXDMA_CFG_BASE	RXDMA_CFG_RINGSZ_256
#elif RX_RING_SIZE == 512
#define RXDMA_CFG_BASE	RXDMA_CFG_RINGSZ_512
#elif RX_RING_SIZE == 1024
#define RXDMA_CFG_BASE	RXDMA_CFG_RINGSZ_1K
#elif RX_RING_SIZE == 2048
#define RXDMA_CFG_BASE	RXDMA_CFG_RINGSZ_2K
#elif RX_RING_SIZE == 4096
#define RXDMA_CFG_BASE	RXDMA_CFG_RINGSZ_4K
#elif RX_RING_SIZE == 8192
#define RXDMA_CFG_BASE	RXDMA_CFG_RINGSZ_8K
#else
#error RX_RING_SIZE is illegal...
#endif

#define NEXT_TX(N)	(((N) + 1) & (TX_RING_SIZE - 1))
#define NEXT_RX(N)	(((N) + 1) & (RX_RING_SIZE - 1))

#define TX_BUFFS_AVAIL(GP)					\
	(((GP)->tx_old <= (GP)->tx_new) ?			\
	  (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new :	\
	  (GP)->tx_old - (GP)->tx_new - 1)

#define RX_OFFSET          2
#define RX_BUF_ALLOC_SIZE(gp)	((gp)->dev->mtu + 46 + RX_OFFSET + 64)

#define RX_COPY_THRESHOLD  256

#if TX_RING_SIZE < 128
#define INIT_BLOCK_TX_RING_SIZE		128
#else
#define INIT_BLOCK_TX_RING_SIZE		TX_RING_SIZE
#endif

#if RX_RING_SIZE < 128
#define INIT_BLOCK_RX_RING_SIZE		128
#else
#define INIT_BLOCK_RX_RING_SIZE		RX_RING_SIZE
#endif

struct gem_init_block {
	struct gem_txd	txd[INIT_BLOCK_TX_RING_SIZE];
	struct gem_rxd	rxd[INIT_BLOCK_RX_RING_SIZE];
};

enum gem_phy_type {
	phy_mii_mdio0,
	phy_mii_mdio1,
	phy_serialink,
	phy_serdes,
};

enum gem_phy_model {
	phymod_generic,
	phymod_bcm5201,
	phymod_bcm5221,
	phymod_bcm5400,
	phymod_bcm5401,
	phymod_bcm5411,
	phymod_m1011,
};

enum link_state {
	link_down = 0,	/* No link, will retry */
	link_aneg,	/* Autoneg in progress */
	link_force_try,	/* Try Forced link speed */
	link_force_ret,	/* Forced mode worked, retrying autoneg */
	link_force_ok,	/* Stay in forced mode */
	link_up		/* Link is up */
};

struct gem {
	spinlock_t lock;
	unsigned long regs;
	int rx_new, rx_old;
	int tx_new, tx_old;

	/* Set when chip is actually in operational state
	 * (ie. not power managed)
	 */
	int hw_running;
	int opened;
	struct semaphore pm_sem;
	struct tq_struct pm_task;
	struct timer_list pm_timer;

	struct gem_init_block *init_block;

	struct sk_buff *rx_skbs[RX_RING_SIZE];
	struct sk_buff *tx_skbs[RX_RING_SIZE];

	u32			msg_enable;

	struct net_device_stats net_stats;

	enum gem_phy_type	phy_type;
	enum gem_phy_model	phy_mod;
	int			tx_fifo_sz;
	int			rx_fifo_sz;
	int			rx_pause_off;
	int			rx_pause_on;
	int			mii_phy_addr;
	int			gigabit_capable;

	/* Autoneg & PHY control */
	int			link_cntl;
	int			link_advertise;
	int			link_fcntl;
	enum link_state		lstate;
	struct timer_list	link_timer;
	int			timer_ticks;
	int			wake_on_lan;
	struct tq_struct	reset_task;
	volatile int		reset_task_pending;
	
	/* Diagnostic counters and state. */
	u64			pause_entered;
	u16			pause_last_time_recvd;

	dma_addr_t gblock_dvma;
	struct pci_dev *pdev;
	struct net_device *dev;
#ifdef CONFIG_ALL_PPC
	struct device_node	*of_node;
#endif
};

#define ALIGNED_RX_SKB_ADDR(addr) \
        ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
static __inline__ struct sk_buff *gem_alloc_skb(int size, int gfp_flags)
{
	struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);

	if (skb) {
		int offset = (int) ALIGNED_RX_SKB_ADDR(skb->data);
		if (offset)
			skb_reserve(skb, offset);
	}

	return skb;
}

#endif /* _SUNGEM_H */