sungem.h

linux和2410结合开发 用他可以生成2410所需的zImage文件

/* Send Pause Command. */
#define MAC_SNDPAUSE_TS	0x0000ffff	/* The pause_time operand used in
					 * Send_Pause and flow-control
					 * handshakes.
					 */
#define MAC_SNDPAUSE_SP	0x00010000	/* Setting this bit instructs the MAC
					 * to send a Pause Flow Control
					 * frame onto the network.
					 */

/* TX MAC Status Register. */
#define MAC_TXSTAT_XMIT	0x00000001	/* Frame Transmitted		*/
#define MAC_TXSTAT_URUN	0x00000002	/* TX Underrun			*/
#define MAC_TXSTAT_MPE	0x00000004	/* Max Packet Size Error	*/
#define MAC_TXSTAT_NCE	0x00000008	/* Normal Collision Cntr Expire	*/
#define MAC_TXSTAT_ECE	0x00000010	/* Excess Collision Cntr Expire	*/
#define MAC_TXSTAT_LCE	0x00000020	/* Late Collision Cntr Expire	*/
#define MAC_TXSTAT_FCE	0x00000040	/* First Collision Cntr Expire	*/
#define MAC_TXSTAT_DTE	0x00000080	/* Defer Timer Expire		*/
#define MAC_TXSTAT_PCE	0x00000100	/* Peak Attempts Cntr Expire	*/

/* RX MAC Status Register. */
#define MAC_RXSTAT_RCV	0x00000001	/* Frame Received		*/
#define MAC_RXSTAT_OFLW	0x00000002	/* Receive Overflow		*/
#define MAC_RXSTAT_FCE	0x00000004	/* Frame Cntr Expire		*/
#define MAC_RXSTAT_ACE	0x00000008	/* Align Error Cntr Expire	*/
#define MAC_RXSTAT_CCE	0x00000010	/* CRC Error Cntr Expire	*/
#define MAC_RXSTAT_LCE	0x00000020	/* Length Error Cntr Expire	*/
#define MAC_RXSTAT_VCE	0x00000040	/* Code Violation Cntr Expire	*/

/* MAC Control Status Register. */
#define MAC_CSTAT_PRCV	0x00000001	/* Pause Received		*/
#define MAC_CSTAT_PS	0x00000002	/* Paused State			*/
#define MAC_CSTAT_NPS	0x00000004	/* Not Paused State		*/
#define MAC_CSTAT_PTR	0xffff0000	/* Pause Time Received		*/

/* The layout of the MAC_{TX,RX,C}MASK registers is identical to that
 * of MAC_{TX,RX,C}STAT.  Bits set in MAC_{TX,RX,C}MASK will prevent
 * that interrupt type from being signalled to front end of GEM.  For
 * the interrupt to actually get sent to the cpu, it is necessary to
 * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well.
 */

/* TX MAC Configuration Register.
 *
 * NOTE: The TX MAC Enable bit must be cleared and polled until
 *	 zero before any other bits in this register are changed.
 *
 *	 Also, enabling the Carrier Extension feature of GEM is
 *	 a 3 step process 1) Set TX Carrier Extension 2) Set
 *	 RX Carrier Extension 3) Set Slot Time to 0x200.  This
 *	 mode must be enabled when in half-duplex at 1Gbps, else
 *	 it must be disabled.
 */
#define MAC_TXCFG_ENAB	0x00000001	/* TX MAC Enable		*/
#define MAC_TXCFG_ICS	0x00000002	/* Ignore Carrier Sense		*/
#define MAC_TXCFG_ICOLL	0x00000004	/* Ignore Collisions		*/
#define MAC_TXCFG_EIPG0	0x00000008	/* Enable IPG0			*/
#define MAC_TXCFG_NGU	0x00000010	/* Never Give Up		*/
#define MAC_TXCFG_NGUL	0x00000020	/* Never Give Up Limit		*/
#define MAC_TXCFG_NBO	0x00000040	/* No Backoff			*/
#define MAC_TXCFG_SD	0x00000080	/* Slow Down			*/
#define MAC_TXCFG_NFCS	0x00000100	/* No FCS			*/
#define MAC_TXCFG_TCE	0x00000200	/* TX Carrier Extension		*/

/* RX MAC Configuration Register.
 *
 * NOTE: The RX MAC Enable bit must be cleared and polled until
 *	 zero before any other bits in this register are changed.
 *
 *	 Similar rules apply to the Hash Filter Enable bit when
 *	 programming the hash table registers, and the Address Filter
 *	 Enable bit when programming the address filter registers.
 */
#define MAC_RXCFG_ENAB	0x00000001	/* RX MAC Enable		*/
#define MAC_RXCFG_SPAD	0x00000002	/* Strip Pad			*/
#define MAC_RXCFG_SFCS	0x00000004	/* Strip FCS			*/
#define MAC_RXCFG_PROM	0x00000008	/* Promiscuous Mode		*/
#define MAC_RXCFG_PGRP	0x00000010	/* Promiscuous Group		*/
#define MAC_RXCFG_HFE	0x00000020	/* Hash Filter Enable		*/
#define MAC_RXCFG_AFE	0x00000040	/* Address Filter Enable	*/
#define MAC_RXCFG_DDE	0x00000080	/* Disable Discard on Error	*/
#define MAC_RXCFG_RCE	0x00000100	/* RX Carrier Extension		*/

/* MAC Control Config Register. */
#define MAC_MCCFG_SPE	0x00000001	/* Send Pause Enable		*/
#define MAC_MCCFG_RPE	0x00000002	/* Receive Pause Enable		*/
#define MAC_MCCFG_PMC	0x00000004	/* Pass MAC Control		*/

/* XIF Configuration Register.
 *
 * NOTE: When leaving or entering loopback mode, a global hardware
 *       init of GEM should be performed.
 */
#define MAC_XIFCFG_OE	0x00000001	/* MII TX Output Driver Enable	*/
#define MAC_XIFCFG_LBCK	0x00000002	/* Loopback TX to RX		*/
#define MAC_XIFCFG_DISE	0x00000004	/* Disable RX path during TX	*/
#define MAC_XIFCFG_GMII	0x00000008	/* Use GMII clocks + datapath	*/
#define MAC_XIFCFG_MBOE	0x00000010	/* Controls MII_BUF_EN pin	*/
#define MAC_XIFCFG_LLED	0x00000020	/* Force LINKLED# active (low)	*/
#define MAC_XIFCFG_FLED	0x00000040	/* Force FDPLXLED# active (low)	*/

/* InterPacketGap0 Register.  This 8-bit value is used as an extension
 * to the InterPacketGap1 Register.  Specifically it contributes to the
 * timing of the RX-to-TX IPG.  This value is ignored and presumed to
 * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit
 * is cleared in the TX MAC Configuration Register.
 *
 * This value in this register in terms of media byte time.
 *
 * Recommended value: 0x00
 */

/* InterPacketGap1 Register.  This 8-bit value defines the first 2/3
 * portion of the Inter Packet Gap.
 *
 * This value in this register in terms of media byte time.
 *
 * Recommended value: 0x08
 */

/* InterPacketGap2 Register.  This 8-bit value defines the second 1/3
 * portion of the Inter Packet Gap.
 *
 * This value in this register in terms of media byte time.
 *
 * Recommended value: 0x04
 */

/* Slot Time Register.  This 10-bit value specifies the slot time
 * parameter in units of media byte time.  It determines the physical
 * span of the network.
 *
 * Recommended value: 0x40
 */

/* Minimum Frame Size Register.  This 10-bit register specifies the
 * smallest sized frame the TXMAC will send onto the medium, and the
 * RXMAC will receive from the medium.
 *
 * Recommended value: 0x40
 */

/* Maximum Frame and Burst Size Register.
 *
 * This register specifies two things.  First it specifies the maximum
 * sized frame the TXMAC will send and the RXMAC will recognize as
 * valid.  Second, it specifies the maximum run length of a burst of
 * packets sent in half-duplex gigabit modes.
 *
 * Recommended value: 0x200005ee
 */
#define MAC_MAXFSZ_MFS	0x00007fff	/* Max Frame Size		*/
#define MAC_MAXFSZ_MBS	0x7fff0000	/* Max Burst Size		*/

/* PA Size Register.  This 10-bit register specifies the number of preamble
 * bytes which will be transmitted at the beginning of each frame.  A
 * value of two or greater should be programmed here.
 *
 * Recommended value: 0x07
 */

/* Jam Size Register.  This 4-bit register specifies the duration of
 * the jam in units of media byte time.
 *
 * Recommended value: 0x04
 */

/* Attempts Limit Register.  This 8-bit register specifies the number
 * of attempts that the TXMAC will make to transmit a frame, before it
 * resets its Attempts Counter.  After reaching the Attempts Limit the
 * TXMAC may or may not drop the frame, as determined by the NGU
 * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC
 * Configuration Register.
 *
 * Recommended value: 0x10
 */

/* MAX Control Type Register.  This 16-bit register specifies the
 * "type" field of a MAC Control frame.  The TXMAC uses this field to
 * encapsulate the MAC Control frame for transmission, and the RXMAC
 * uses it for decoding valid MAC Control frames received from the
 * network.
 *
 * Recommended value: 0x8808
 */

/* MAC Address Registers.  Each of these registers specify the
 * ethernet MAC of the interface, 16-bits at a time.  Register
 * 0 specifies bits [47:32], register 1 bits [31:16], and register
 * 2 bits [15:0].
 *
 * Registers 3 through and including 5 specify an alternate
 * MAC address for the interface.
 *
 * Registers 6 through and including 8 specify the MAC Control
 * Address, which must be the reserved multicast address for MAC
 * Control frames.
 *
 * Example: To program primary station address a:b:c:d:e:f into
 *	    the chip.
 *		MAC_Address_2 = (a << 8) | b
 *		MAC_Address_1 = (c << 8) | d
 *		MAC_Address_0 = (e << 8) | f
 */

/* Address Filter Registers.  Registers 0 through 2 specify bit
 * fields [47:32] through [15:0], respectively, of the address
 * filter.  The Address Filter 2&1 Mask Register denotes the 8-bit
 * nibble mask for Address Filter Registers 2 and 1.  The Address
 * Filter 0 Mask Register denotes the 16-bit mask for the Address
 * Filter Register 0.
 */

/* Hash Table Registers.  Registers 0 through 15 specify bit fields
 * [255:240] through [15:0], respectively, of the hash table.
 */

/* Statistics Registers.  All of these registers are 16-bits and
 * track occurances of a specific event.  GEM can be configured
 * to interrupt the host cpu when any of these counters overflow.
 * They should all be explicitly initialized to zero when the interface
 * is brought up.
 */

/* Random Number Seed Register.  This 10-bit value is used as the
 * RNG seed inside GEM for the CSMA/CD backoff algorithm.  It is
 * recommended to program this register to the 10 LSB of the
 * interfaces MAC address.
 */

/* Pause Timer, read-only.  This 16-bit timer is used to time the pause
 * interval as indicated by a received pause flow control frame.
 * A non-zero value in this timer indicates that the MAC is currently in
 * the paused state.
 */

/* MIF Registers */
#define MIF_BBCLK	0x6200UL	/* MIF Bit-Bang Clock		*/
#define MIF_BBDATA	0x6204UL	/* MIF Bit-Band Data		*/
#define MIF_BBOENAB	0x6208UL	/* MIF Bit-Bang Output Enable	*/
#define MIF_FRAME	0x620CUL	/* MIF Frame/Output Register	*/
#define MIF_CFG		0x6210UL	/* MIF Configuration Register	*/
#define MIF_MASK	0x6214UL	/* MIF Mask Register		*/
#define MIF_STATUS	0x6218UL	/* MIF Status Register		*/
#define MIF_SMACHINE	0x621CUL	/* MIF State Machine Register	*/

/* MIF Bit-Bang Clock.  This 1-bit register is used to generate the
 * MDC clock waveform on the MII Management Interface when the MIF is
 * programmed in the "Bit-Bang" mode.  Writing a '1' after a '0' into
 * this register will create a rising edge on the MDC, while writing
 * a '0' after a '1' will create a falling edge.  For every bit that
 * is transferred on the management interface, both edges have to be
 * generated.
 */

/* MIF Bit-Bang Data.  This 1-bit register is used to generate the
 * outgoing data (MDO) on the MII Management Interface when the MIF
 * is programmed in the "Bit-Bang" mode.  The daa will be steered to the
 * appropriate MDIO based on the state of the PHY_Select bit in the MIF
 * Configuration Register.
 */

/* MIF Big-Band Output Enable.  THis 1-bit register is used to enable
 * ('1') or disable ('0') the I-directional driver on the MII when the
 * MIF is programmed in the "Bit-Bang" mode.  The MDIO should be enabled
 * when data bits are transferred from the MIF to the transceiver, and it
 * should be disabled when the interface is idle or when data bits are
 * transferred from the transceiver to the MIF (data portion of a read
 * instruction).  Only one MDIO will be enabled at a given time, depending
 * on the state of the PHY_Select bit in the MIF Configuration Register.
 */

/* MIF Configuration Register.  This 15-bit register controls the operation
 * of the MIF.
 */
#define MIF_CFG_PSELECT	0x00000001	/* Xcvr slct: 0=mdio0 1=mdio1	*/
#define MIF_CFG_POLL	0x00000002	/* Enable polling mechanism	*/
#define MIF_CFG_BBMODE	0x00000004	/* 1=bit-bang 0=frame mode	*/
#define MIF_CFG_PRADDR	0x000000f8	/* Xcvr poll register address	*/
#define MIF_CFG_MDI0	0x00000100	/* MDIO_0 present or read-bit	*/
#define MIF_CFG_MDI1	0x00000200	/* MDIO_1 present or read-bit	*/
#define MIF_CFG_PPADDR	0x00007c00	/* Xcvr poll PHY address	*/

/* MIF Frame/Output Register.  This 32-bit register allows the host to
 * communicate with a transceiver in frame mode (as opposed to big-bang
 * mode).  Writes by the host specify an instrution.  After being issued
 * the host must poll this register for completion.  Also, after
 * completion this register holds the data returned by the transceiver
 * if applicable.
 */
#define MIF_FRAME_ST	0xc0000000	/* STart of frame		*/
#define MIF_FRAME_OP	0x30000000	/* OPcode			*/
#define MIF_FRAME_PHYAD	0x0f800000	/* PHY ADdress			*/
#define MIF_FRAME_REGAD	0x007c0000	/* REGister ADdress		*/
#define MIF_FRAME_TAMSB	0x00020000	/* Turn Around MSB		*/
#define MIF_FRAME_TALSB	0x00010000	/* Turn Around LSB		*/
#define MIF_FRAME_DATA	0x0000ffff	/* Instruction Payload		*/

/* MIF Status Register.  This register reports status when the MIF is
 * operating in the poll mode.  The poll status field is auto-clearing
 * on read.
 */
#define MIF_STATUS_DATA	0xffff0000	/* Live image of XCVR reg	*/
#define MIF_STATUS_STAT	0x0000ffff	/* Which bits have changed	*/

/* MIF Mask Register.  This 16-bit register is used when in poll mode
 * to say which bits of the polled register will cause an interrupt
 * when changed.
 */

/* PCS/Serialink Registers */
#define PCS_MIICTRL	0x9000UL	/* PCS MII Control Register	*/
#define PCS_MIISTAT	0x9004UL	/* PCS MII Status Register	*/
#define PCS_MIIADV	0x9008UL	/* PCS MII Advertisement Reg	*/
#define PCS_MIILP	0x900CUL	/* PCS MII Link Partner Ability	*/
#define PCS_CFG		0x9010UL	/* PCS Configuration Register	*/
#define PCS_SMACHINE	0x9014UL	/* PCS State Machine Register	*/
#define PCS_ISTAT	0x9018UL	/* PCS Interrupt Status Reg	*/
#define PCS_DMODE	0x9050UL	/* Datapath Mode Register	*/
#define PCS_SCTRL	0x9054UL	/* Serialink Control Register	*/
#define PCS_SOS		0x9058UL	/* Shared Output Select Reg	*/
#define PCS_SSTATE	0x905CUL	/* Serialink State Register	*/

/* PCD MII Control Register. */
#define PCS_MIICTRL_SPD	0x00000040	/* Read as one, writes ignored	*/
#define PCS_MIICTRL_CT	0x00000080	/* Force COL signal active	*/
#define PCS_MIICTRL_DM	0x00000100	/* Duplex mode, forced low	*/
#define PCS_MIICTRL_RAN	0x00000200	/* Restart auto-neg, self clear	*/
#define PCS_MIICTRL_ISO	0x00000400	/* Read as zero, writes ignored	*/
#define PCS_MIICTRL_PD	0x00000800	/* Read as zero, writes ignored	*/
#define PCS_MIICTRL_ANE	0x00001000	/* Auto-neg enable		*/
#define PCS_MIICTRL_SS	0x00002000	/* Read as zero, writes ignored	*/
#define PCS_MIICTRL_WB	0x00004000	/* Wrapback, loopback at 10-bit
					 * input side of Serialink
					 */
#define PCS_MIICTRL_RST	0x00008000	/* Resets PCS, self clearing	*/

/* PCS MII Status Register. */
#define PCS_MIISTAT_EC	0x00000001	/* Ext Capability: Read as zero	*/
#define PCS_MIISTAT_JD	0x00000002	/* Jabber Detect: Read as zero	*/
#define PCS_MIISTAT_LS	0x00000004	/* Link Status: 1=up 0=down	*/
#define PCS_MIISTAT_ANA	0x00000008	/* Auto-neg Ability, always 1	*/