gmac.h

linux和2410结合开发 用他可以生成2410所需的zImage文件

#define GM_MAC_CTRLSTAT_PAUSE_NOT	0x00000004
#define GM_MAC_CTRLSTAT_PAUSE_TIM_MASK	0xffff0000
#define GM_MAC_CTRLSTAT_PAUSE_TIM_SHIFT	16

/* -- 0x6020		MAC Tx mask
 * 			Same bits as MAC Tx status
 */
#define GM_MAC_TX_MASK			(0x6020 | REG_SZ_16)

/* -- 0x6024		MAC Rx mask
 * 			Same bits as MAC Rx status
 */
#define GM_MAC_RX_MASK			(0x6024 | REG_SZ_16)

/* -- 0x6028		MAC Control/Status mask
 * 			Same bits as MAC control/status low order byte
 */
#define GM_MAC_CTRLSTAT_MASK		(0x6024 | REG_SZ_8)

/* -- 0x6030		MAC Tx configuration
 */
#define GM_MAC_TX_CONFIG		(0x6030 | REG_SZ_16)
#define GM_MAC_TX_CONF_ENABLE		0x0001
#define GM_MAC_TX_CONF_IGNORE_CARRIER	0x0002
#define GM_MAC_TX_CONF_IGNORE_COLL	0x0004
#define GM_MAC_TX_CONF_ENABLE_IPG0	0x0008
#define GM_MAC_TX_CONF_DONT_GIVEUP	0x0010
#define GM_MAC_TX_CONF_DONT_GIVEUP_NLMT	0x0020
#define GM_MAC_TX_CONF_NO_BACKOFF	0x0040
#define GM_MAC_TX_CONF_SLOWDOWN		0x0080
#define GM_MAC_TX_CONF_NO_FCS		0x0100
#define GM_MAC_TX_CONF_CARRIER_EXT	0x0200

/* -- 0x6034		MAC Rx configuration
 */
#define GM_MAC_RX_CONFIG		(0x6034 | REG_SZ_16)
#define GM_MAC_RX_CONF_ENABLE		0x0001
#define GM_MAC_RX_CONF_STRIP_PAD	0x0002
#define GM_MAC_RX_CONF_STIP_FCS		0x0004
#define GM_MAC_RX_CONF_RX_ALL		0x0008
#define GM_MAC_RX_CONF_RX_ALL_MULTI	0x0010
#define GM_MAC_RX_CONF_HASH_ENABLE	0x0020
#define GM_MAC_RX_CONF_ADDR_FLTR_ENABLE	0x0040
#define GM_MAC_RX_CONF_PASS_ERROR_FRAM	0x0080
#define GM_MAC_RX_CONF_CARRIER_EXT	0x0100

/* -- 0x6038		MAC control configuration
 */
#define GM_MAC_CTRL_CONFIG		(0x6038 | REG_SZ_8)
#define GM_MAC_CTRL_CONF_SND_PAUSE_EN	0x01
#define GM_MAC_CTRL_CONF_RCV_PAUSE_EN	0x02
#define GM_MAC_CTRL_CONF_PASS_CTRL_FRAM	0x04

/* -- 0x603c		MAC XIF configuration */
#define GM_MAC_XIF_CONFIG		(0x603c | REG_SZ_8)
#define GM_MAC_XIF_CONF_TX_MII_OUT_EN	0x01
#define GM_MAC_XIF_CONF_MII_INT_LOOP	0x02
#define GM_MAC_XIF_CONF_DISABLE_ECHO	0x04
#define GM_MAC_XIF_CONF_GMII_MODE	0x08
#define GM_MAC_XIF_CONF_MII_BUFFER_EN	0x10
#define GM_MAC_XIF_CONF_LINK_LED	0x20
#define GM_MAC_XIF_CONF_FULL_DPLX_LED	0x40

/* -- 0x6040		MAC inter-packet GAP 0
 */
#define GM_MAC_INTR_PKT_GAP0		(0x6040 | REG_SZ_8)
#define GM_MAC_INTR_PKT_GAP0_DEFAULT	0x00

/* -- 0x6044		MAC inter-packet GAP 1
 */
#define GM_MAC_INTR_PKT_GAP1		(0x6044 | REG_SZ_8)
#define GM_MAC_INTR_PKT_GAP1_DEFAULT	0x08

/* -- 0x6048		MAC inter-packet GAP 2
 */
#define GM_MAC_INTR_PKT_GAP2		(0x6048 | REG_SZ_8)
#define GM_MAC_INTR_PKT_GAP2_DEFAULT	0x04

/* -- 604c		MAC slot time
 */
#define GM_MAC_SLOT_TIME		(0x604C | REG_SZ_16)
#define GM_MAC_SLOT_TIME_DEFAULT	0x0040

/* -- 6050		MAC minimum frame size
 */
#define GM_MAC_MIN_FRAME_SIZE		(0x6050 | REG_SZ_16)
#define GM_MAC_MIN_FRAME_SIZE_DEFAULT	0x0040

/* -- 6054		MAC maximum frame size
 */
#define GM_MAC_MAX_FRAME_SIZE		(0x6054 | REG_SZ_16)
#define GM_MAC_MAX_FRAME_SIZE_DEFAULT	0x05ee
#define GM_MAC_MAX_FRAME_SIZE_ALIGN	0x5f0

/* -- 6058		MAC preamble length
 */
#define GM_MAC_PREAMBLE_LEN		(0x6058 | REG_SZ_16)
#define GM_MAC_PREAMBLE_LEN_DEFAULT	0x0007

/* -- 605c		MAC jam size
 */
#define GM_MAC_JAM_SIZE			(0x605c | REG_SZ_8)
#define GM_MAC_JAM_SIZE_DEFAULT		0x04

/* -- 6060		MAC attempt limit
 */
#define GM_MAC_ATTEMPT_LIMIT		(0x6060 | REG_SZ_8)
#define GM_MAC_ATTEMPT_LIMIT_DEFAULT	0x10

/* -- 6064		MAC control type
 */
#define GM_MAC_CONTROL_TYPE		(0x6064 | REG_SZ_16)
#define GM_MAC_CONTROL_TYPE_DEFAULT	0x8808

/* -- 6080		MAC address 15..0
 * -- 6084		MAC address 16..31
 * -- 6088		MAC address 32..47
 */
#define GM_MAC_ADDR_NORMAL0		(0x6080 | REG_SZ_16)
#define GM_MAC_ADDR_NORMAL1		(0x6084 | REG_SZ_16)
#define GM_MAC_ADDR_NORMAL2		(0x6088 | REG_SZ_16)

/* -- 608c		MAC alternate address 15..0
 * -- 6090		MAC alternate address 16..31
 * -- 6094		MAC alternate address 32..47
 */
#define GM_MAC_ADDR_ALT0		(0x608c | REG_SZ_16)
#define GM_MAC_ADDR_ALT1		(0x6090 | REG_SZ_16)
#define GM_MAC_ADDR_ALT2		(0x6094 | REG_SZ_16)

/* -- 6098		MAC control address 15..0
 * -- 609c		MAC control address 16..31
 * -- 60a0		MAC control address 32..47
 */
#define GM_MAC_ADDR_CTRL0		(0x6098 | REG_SZ_16)
#define GM_MAC_ADDR_CTRL1		(0x609c | REG_SZ_16)
#define GM_MAC_ADDR_CTRL2		(0x60a0 | REG_SZ_16)

/* -- 60a4		MAC address filter (0_0)
 * -- 60a8		MAC address filter (0_1)
 * -- 60ac		MAC address filter (0_2)
 */
#define GM_MAC_ADDR_FILTER0		(0x60a4 | REG_SZ_16)
#define GM_MAC_ADDR_FILTER1		(0x60a8 | REG_SZ_16)
#define GM_MAC_ADDR_FILTER2		(0x60ac | REG_SZ_16)

/* -- 60b0		MAC address filter mask 1,2
 */
#define GM_MAC_ADDR_FILTER_MASK1_2	(0x60b0 | REG_SZ_8)

/* -- 60b4		MAC address filter mask 0
 */
#define GM_MAC_ADDR_FILTER_MASK0	(0x60b4 | REG_SZ_16)

/* -- [60c0 .. 60fc]	MAC hash table
 */
#define GM_MAC_ADDR_FILTER_HASH0	(0x60c0 | REG_SZ_16)

/* -- 6100		MAC normal collision counter
 */
#define GM_MAC_COLLISION_CTR		(0x6100 | REG_SZ_16)

/* -- 6104		MAC 1st successful collision counter
 */
#define GM_MAC_FIRST_COLLISION_CTR	(0x6104 | REG_SZ_16)

/* -- 6108		MAC excess collision counter
 */
#define GM_MAC_EXCS_COLLISION_CTR	(0x6108 | REG_SZ_16)

/* -- 610c		MAC late collision counter
 */
#define GM_MAC_LATE_COLLISION_CTR	(0x610c | REG_SZ_16)

/* -- 6110		MAC defer timer counter
 */
#define GM_MAC_DEFER_TIMER_COUNTER	(0x6110 | REG_SZ_16)

/* -- 6114		MAC peak attempts
 */
#define GM_MAC_PEAK_ATTEMPTS		(0x6114 | REG_SZ_16)

/* -- 6118		MAC Rx frame counter
 */
#define GM_MAC_RX_FRAME_CTR		(0x6118 | REG_SZ_16)

/* -- 611c		MAC Rx length error counter
 */
#define GM_MAC_RX_LEN_ERR_CTR		(0x611c | REG_SZ_16)

/* -- 6120		MAC Rx alignment error counter
 */
#define GM_MAC_RX_ALIGN_ERR_CTR		(0x6120 | REG_SZ_16)

/* -- 6124		MAC Rx CRC error counter
 */
#define GM_MAC_RX_CRC_ERR_CTR		(0x6124 | REG_SZ_16)

/* -- 6128		MAC Rx code violation error counter
 */
#define GM_MAC_RX_CODE_VIOLATION_CTR	(0x6128 | REG_SZ_16)

/* -- 6130		MAC random number seed
 */
#define GM_MAC_RANDOM_SEED		(0x6130 | REG_SZ_16)

/* -- 6134		MAC state machine
 */
#define GM_MAC_STATE_MACHINE		(0x6134 | REG_SZ_8)


	/*
	 * MIF registers
	 */


/* -- 0x6200	RW	MIF bit bang clock
 */
#define GM_MIF_BB_CLOCK			(0x6200 | REG_SZ_8)

/* -- 0x6204	RW	MIF bit bang data
 */
#define GM_MIF_BB_DATA			(0x6204 | REG_SZ_8)

/* -- 0x6208	RW	MIF bit bang output enable
 */
#define GM_MIF_BB_OUT_ENABLE		(0x6208 | REG_SZ_8)

/* -- 0x620c	RW	MIF frame control & data
 */
#define GM_MIF_FRAME_CTL_DATA		(0x620c | REG_SZ_32)
#define GM_MIF_FRAME_START_MASK		0xc0000000
#define GM_MIF_FRAME_START_SHIFT	30
#define GM_MIF_FRAME_OPCODE_MASK	0x30000000
#define GM_MIF_FRAME_OPCODE_SHIFT	28
#define GM_MIF_FRAME_PHY_ADDR_MASK	0x0f800000
#define GM_MIF_FRAME_PHY_ADDR_SHIFT	23
#define GM_MIF_FRAME_REG_ADDR_MASK	0x007c0000
#define GM_MIF_FRAME_REG_ADDR_SHIFT	18
#define GM_MIF_FRAME_TURNAROUND_HI	0x00020000
#define GM_MIF_FRAME_TURNAROUND_LO	0x00010000
#define GM_MIF_FRAME_DATA_MASK		0x0000ffff
#define GM_MIF_FRAME_DATA_SHIFT		0

/* -- 0x6210	RW	MIF config reg
 */
#define GM_MIF_CFG			(0x6210 | REG_SZ_16)
#define	GM_MIF_CFGPS			0x00000001	/* PHY Select */
#define	GM_MIF_CFGPE			0x00000002	/* Poll Enable */
#define	GM_MIF_CFGBB			0x00000004	/* Bit Bang Enable */
#define	GM_MIF_CFGPR_MASK		0x000000f8	/* Poll Register address */
#define	GM_MIF_CFGPR_SHIFT		3
#define	GM_MIF_CFGM0			0x00000100	/* MDIO_0 Data / MDIO_0 attached */
#define	GM_MIF_CFGM1			0x00000200	/* MDIO_1 Data / MDIO_1 attached */
#define	GM_MIF_CFGPD_MASK		0x00007c00	/* Poll Device PHY address */
#define	GM_MIF_CFGPD_SHIFT		10

#define	GM_MIF_POLL_DELAY		200

#define	GM_INTERNAL_PHYAD		1		/* PHY address for int. transceiver */
#define	GM_EXTERNAL_PHYAD		0		/* PHY address for ext. transceiver */

/* -- 0x6214	RW	MIF interrupt mask reg
 *			same as basic/status Register
 */
#define GM_MIF_IRQ_MASK			(0x6214 | REG_SZ_16)

/* -- 0x6218	RW	MIF basic/status reg
 *			The Basic portion of this register indicates the last
 *			value of the register read indicated in the POLL REG field
 *			of the Configuration Register.
 *			The Status portion indicates bit(s) that have changed.
 *			The MIF Mask register is corresponding to this register in
 *			terms of the bit(s) that need to be masked for generating
 *			interrupt on the MIF Interrupt Bit of the Global Status Rgister.
 */
#define GM_MIF_STATUS			(0x6218 | REG_SZ_32)

#define	GM_MIF_STATUS_MASK		0x0000ffff	/* 0-15 : Status */
#define	GM_MIF_BASIC_MASK		0xffff0000	/* 16-31 : Basic register */

	/*
	 * PCS link registers
	 */

/* -- 0x9000	RW	PCS mii control reg
 */
#define GM_PCS_CONTROL			(0x9000 | REG_SZ_16)

/* -- 0x9004	RW	PCS mii status reg
 */
#define GM_PCS_STATUS			(0x9004 | REG_SZ_16)

/* -- 0x9008	RW	PCS mii advertisement
 */
#define GM_PCS_ADVERTISEMENT		(0x9008 | REG_SZ_16)

/* -- 0x900c	RW	PCS mii LP ability
 */
#define GM_PCS_ABILITY			(0x900c | REG_SZ_16)

/* -- 0x9010	RW	PCS config
 */
#define GM_PCS_CONFIG			(0x9010 | REG_SZ_8)

/* -- 0x9014	RW	PCS state machine
 */
#define GM_PCS_STATE_MACHINE		(0x9014 | REG_SZ_32)

/* -- 0x9018	RW	PCS interrupt status
 */
#define GM_PCS_IRQ_STATUS		(0x9018 | REG_SZ_8)

/* -- 0x9050	RW	PCS datapath mode
 */
#define GM_PCS_DATAPATH_MODE		(0x9050 | REG_SZ_8)