hd6457x.c

linux和2410结合开发 用他可以生成2410所需的zImage文件

		desc = desc_address(port, port->txlast, 1);
		len = readw(&desc->len);

		port->hdlc.stats.tx_packets++;
		port->hdlc.stats.tx_bytes += len;
		writeb(0, &desc->stat);	/* Free descriptor */

		port->txlast = (port->txlast + 1) %
			port_to_card(port)->ring_buffers;
	}

	netif_wake_queue(hdlc_to_dev(&port->hdlc));
	spin_unlock(&port->lock);
}



static void sca_intr(int irq, void* dev_id, struct pt_regs *regs)
{
	card_t *card = dev_id;
	int boguscnt = INTR_WORK;
	int i;
	u8 stat;

#ifndef ALL_PAGES_ALWAYS_MAPPED
	u8 page = sca_get_page(card);
#endif

	while((stat = sca_intr_status(card)) != 0) {
		for (i = 0; i < 2; i++) {
			port_t *port = get_port(card, i);
			if (port) {
				if (stat & SCA_INTR_MSCI(i))
					sca_msci_intr(port);

				if (stat & SCA_INTR_DMAC_RX(i))
					sca_rx_intr(port);

				if (stat & SCA_INTR_DMAC_TX(i))
					sca_tx_intr(port);
			}

			if (--boguscnt < 0) {
				printk(KERN_ERR "%s: too much work at "
				       "interrupt\n",
				       hdlc_to_name(&port->hdlc));
				goto exit;
			}
		}
	}

 exit:
#ifndef ALL_PAGES_ALWAYS_MAPPED
	openwin(card, page);		/* Restore original page */
#endif
}



static inline int sca_set_loopback(port_t *port, int line)
{
	card_t* card = port_to_card(port);
	u8 msci = get_msci(port);
	u8 md2 = sca_in(msci + MD2, card);

	switch(line) {
	case LINE_DEFAULT:
		md2 &= ~MD2_LOOPBACK;
		port->line &= ~LINE_LOOPBACK;
		break;

	case LINE_LOOPBACK:
		md2 |= MD2_LOOPBACK;
		port->line |= LINE_LOOPBACK;
		break;

	default:
		return -EINVAL;
	}

	sca_out(md2, msci + MD2, card);
	return 0;
}



static void sca_set_clock(port_t *port)
{
	card_t *card = port_to_card(port);
	u8 msci = get_msci(port);
	unsigned int tmc, br = 10, brv = 1024;

	if (port->clkrate > 0) {
		/* Try lower br for better accuracy*/
		do {
			br--;
			brv >>= 1; /* brv = 2^9 = 512 max in specs */

			/* Baud Rate = CLOCK_BASE / TMC / 2^BR */
			tmc = CLOCK_BASE / (brv * port->clkrate);
		}while(br > 1 && tmc <= 128);

		if (tmc < 1) {
			tmc = 1;
			br = 0;	/* For baud=CLOCK_BASE we use tmc=1 br=0 */
			brv = 1;
		} else if (tmc > 255)
			tmc = 256; /* tmc=0 means 256 - low baud rates */

		port->clkrate = CLOCK_BASE / (brv * tmc);
	} else {
		br = 9; /* Minimum clock rate */
		tmc = 256;	/* 8bit = 0 */
		port->clkrate = CLOCK_BASE / (256 * 512);
	}

	port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
	port->txs = (port->txs & ~CLK_BRG_MASK) | br;
	port->tmc = tmc;

	/* baud divisor - time constant*/
#ifdef __HD64570_H
	sca_out(port->tmc, msci + TMC, card);
#else
	sca_out(port->tmc, msci + TMCR, card);
	sca_out(port->tmc, msci + TMCT, card);
#endif

	/* Set BRG bits */
	sca_out(port->rxs, msci + RXS, card);
	sca_out(port->txs, msci + TXS, card);
}



static void sca_set_hdlc_mode(port_t *port, u8 idle, u8 crc, u8 nrzi)
{
	card_t* card = port_to_card(port);
	u8 msci = get_msci(port);
	u8 md2 = (nrzi ? MD2_NRZI : 0) |
		((port->line & LINE_LOOPBACK) ? MD2_LOOPBACK : 0);
	u8 ctl = (idle ? CTL_IDLE : 0);
#ifdef __HD64572_H
	ctl |= CTL_URCT | CTL_URSKP; /* Skip the rest of underrun frame */
#endif

	sca_out(CMD_RESET, msci + CMD, card);
	sca_out(MD0_HDLC | crc, msci + MD0, card);
	sca_out(0x00, msci + MD1, card); /* no address field check */
	sca_out(md2, msci + MD2, card);
	sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
	sca_out(ctl, msci + CTL, card);

#ifdef __HD64570_H
	/* Allow at least 8 bytes before requesting RX DMA operation */
	/* TX with higher priority and possibly with shorter transfers */
	sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
	sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
	sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
#else
	sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
	/* Setting than to larger value may cause Illegal Access */
	sca_out(0x20, msci + TNR0, card); /* =TX DMA activation condition */
	sca_out(0x30, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
	sca_out(0x04, msci + TCR, card); /* =Critical TX DMA activ condition */
#endif


#ifdef __HD64570_H
	/* MSCI TX INT IRQ enable */
	sca_out(IE0_TXINT, msci + IE0, card);
	sca_out(IE1_UDRN, msci + IE1, card); /* TX underrun IRQ */
	sca_out(sca_in(IER0, card) | (phy_node(port) ? 0x80 : 0x08),
		IER0, card);
	/* DMA IRQ enable */
	sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
		IER1, card);
#else
	/* MSCI TX INT and underrrun IRQ enable */
	sca_outl(IE0_TXINT | IE0_UDRN, msci + IE0, card);
	/* DMA & MSCI IRQ enable */
	sca_outl(sca_in(IER0, card) |
		 (phy_node(port) ? 0x02006600 : 0x00020066), IER0, card);
#endif

#ifdef __HD64570_H
	sca_out(port->tmc, msci + TMC, card); /* Restore registers */
#else
	sca_out(port->tmc, msci + TMCR, card);
	sca_out(port->tmc, msci + TMCT, card);
#endif
	sca_out(port->rxs, msci + RXS, card);
	sca_out(port->txs, msci + TXS, card);
	sca_out(CMD_TX_ENABLE, msci + CMD, card);
	sca_out(CMD_RX_ENABLE, msci + CMD, card);
}



#ifdef DEBUG_RINGS
static void sca_dump_rings(hdlc_device *hdlc)
{
	port_t *port = hdlc_to_port(hdlc);
	card_t *card = port_to_card(port);
	u16 cnt;
#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
	u8 page;
#endif

#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
	page = sca_get_page(card);
	openwin(card, 0);
#endif

	printk(KERN_ERR "RX ring: CDA=%u EDA=%u DSR=%02X in=%u "
	       "%sactive",
	       sca_ina(get_dmac_rx(port) + CDAL, card),
	       sca_ina(get_dmac_rx(port) + EDAL, card),
	       sca_in(DSR_RX(phy_node(port)), card),
	       port->rxin,
	       sca_in(DSR_RX(phy_node(port)), card) & DSR_DE?"":"in");
	for (cnt = 0; cnt<port_to_card(port)->ring_buffers; cnt++)
		printk(" %02X",
		       readb(&(desc_address(port, cnt, 0)->stat)));

	printk("\n" KERN_ERR "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
	       "last=%u %sactive",
	       sca_ina(get_dmac_tx(port) + CDAL, card),
	       sca_ina(get_dmac_tx(port) + EDAL, card),
	       sca_in(DSR_TX(phy_node(port)), card), port->txin,
	       port->txlast,
	       sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");

	for (cnt = 0; cnt<port_to_card(port)->ring_buffers; cnt++)
		printk(" %02X",
		       readb(&(desc_address(port, cnt, 1)->stat)));
	printk("\n");

	printk(KERN_ERR "MSCI: MD: %02x %02x %02x, "
	       "ST: %02x %02x %02x %02x"
#ifdef __HD64572_H
	       " %02x"
#endif
	       ", FST: %02x CST: %02x %02x\n",
	       sca_in(get_msci(port) + MD0, card),
	       sca_in(get_msci(port) + MD1, card),
	       sca_in(get_msci(port) + MD2, card),
	       sca_in(get_msci(port) + ST0, card),
	       sca_in(get_msci(port) + ST1, card),
	       sca_in(get_msci(port) + ST2, card),
	       sca_in(get_msci(port) + ST3, card),
#ifdef __HD64572_H
	       sca_in(get_msci(port) + ST4, card),
#endif
	       sca_in(get_msci(port) + FST, card),
	       sca_in(get_msci(port) + CST0, card),
	       sca_in(get_msci(port) + CST1, card));

#ifdef __HD64572_H
	printk(KERN_ERR "ILAR: %02x\n", sca_in(ILAR, card));
#endif

#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
	openwin(card, page); /* Restore original page */
#endif
}
#endif /* DEBUG_RINGS */



static void sca_open(hdlc_device *hdlc)
{
	port_t *port = hdlc_to_port(hdlc);

	sca_set_hdlc_mode(port, 1, MD0_CRC_ITU, 0);
	netif_start_queue(hdlc_to_dev(hdlc));
}


static void sca_close(hdlc_device *hdlc)
{
	port_t *port = hdlc_to_port(hdlc);

	/* reset channel */
	netif_stop_queue(hdlc_to_dev(hdlc));
	sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
}



static int sca_xmit(hdlc_device *hdlc, struct sk_buff *skb)
{
	port_t *port = hdlc_to_port(hdlc);
	struct net_device *dev = hdlc_to_dev(hdlc);
	card_t *card = port_to_card(port);
	pkt_desc *desc;
	u32 buff, len;
#ifndef ALL_PAGES_ALWAYS_MAPPED
	u8 page;
	u32 maxlen;
#endif

	spin_lock_irq(&port->lock);

	desc = desc_address(port, port->txin + 1, 1);
	if (readb(&desc->stat)) { /* allow 1 packet gap */
		/* should never happen - previous xmit should stop queue */
#ifdef DEBUG_PKT
		printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
#endif
		netif_stop_queue(dev);
		spin_unlock_irq(&port->lock);
		return 1;	/* request packet to be queued */
	}

#ifdef DEBUG_PKT
	printk(KERN_DEBUG "%s TX(%i):", hdlc_to_name(hdlc), skb->len);
	debug_frame(skb);
#endif

	desc = desc_address(port, port->txin, 1);
	buff = buffer_offset(port, port->txin, 1);
	len = skb->len;
#ifndef ALL_PAGES_ALWAYS_MAPPED
	page = buff / winsize(card);
	buff = buff % winsize(card);
	maxlen = winsize(card) - buff;

	openwin(card, page);
	if (len > maxlen) {
		memcpy_toio(winbase(card) + buff, skb->data, maxlen);
		openwin(card, page + 1);
		memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
	}
	else
#endif
		memcpy_toio(winbase(card) + buff, skb->data, len);

#if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED)
	openwin(card, 0);	/* select pkt_desc table page back */
#endif
	writew(len, &desc->len);
	writeb(ST_TX_EOM, &desc->stat);
	dev->trans_start = jiffies;

	port->txin = next_desc(port, port->txin);
	sca_outa(desc_offset(port, port->txin, 1),
		 get_dmac_tx(port) + EDAL, card);

	sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */

	desc = desc_address(port, port->txin + 1, 1);
	if (readb(&desc->stat)) /* allow 1 packet gap */
		netif_stop_queue(hdlc_to_dev(&port->hdlc));

	spin_unlock_irq(&port->lock);

	dev_kfree_skb(skb);
	return 0;
}


static void sca_init(card_t *card, int wait_states)
{
	sca_out(wait_states, WCRL, card); /* Wait Control */
	sca_out(wait_states, WCRM, card);
	sca_out(wait_states, WCRH, card);

	sca_out(0, DMER, card);	/* DMA Master disable */
	sca_out(0x03, PCR, card); /* DMA priority */
	sca_out(0, IER1, card);	/* DMA interrupt disable */
	sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
	sca_out(0, DSR_TX(0), card);
	sca_out(0, DSR_RX(1), card);
	sca_out(0, DSR_TX(1), card);
	sca_out(DMER_DME, DMER, card); /* DMA Master enable */
}