ns83820.c

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{
	u32 ethcmd;

	if (copy_from_user(&ethcmd, useraddr, sizeof (ethcmd)))
		return -EFAULT;

	switch (ethcmd) {
	case ETHTOOL_GDRVINFO:
		{
			struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
			strcpy(info.driver, "ns83820");
			strcpy(info.version, VERSION);
			strcpy(info.bus_info, dev->pci_dev->slot_name);
			if (copy_to_user(useraddr, &info, sizeof (info)))
				return -EFAULT;
			return 0;
		}

	/* get link status */
	case ETHTOOL_GLINK: {
		struct ethtool_value edata = { ETHTOOL_GLINK };
		u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;

		if (cfg & CFG_LNKSTS)
			edata.data = 1;
		else
			edata.data = 0;
		if (copy_to_user(useraddr, &edata, sizeof(edata)))
			return -EFAULT;
		return 0;
	}

	default:
		break;
	}

	return -EOPNOTSUPP;
}

static int ns83820_ioctl(struct net_device *_dev, struct ifreq *rq, int cmd)
{
	struct ns83820 *dev = _dev->priv;

	switch(cmd) {
	case SIOCETHTOOL:
		return ns83820_ethtool_ioctl(dev, (void *) rq->ifr_data);

	default:
		return -EOPNOTSUPP;
	}
}

static void ns83820_irq(int foo, void *data, struct pt_regs *regs)
{
	struct ns83820 *dev = data;
	int count = 0;
	u32 isr;
	dprintk("ns83820_irq(%p)\n", dev);

	dev->ihr = 0;

	while (count++ < 32 && (isr = readl(dev->base + ISR))) {
		dprintk("irq: %08x\n", isr);

		if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
			Dprintk("odd isr? 0x%08x\n", isr);

	if ((ISR_RXEARLY | ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr) {
 		if (ISR_RXIDLE & isr) {
			dev->rx_info.idle = 1;
			Dprintk("oh dear, we are idle\n");
		}

		if ((ISR_RXDESC) & isr) {
			rx_irq(dev);
			writel(4, dev->base + IHR);
		}

		if (nr_rx_empty(dev) >= NR_RX_DESC/4) {
			if (dev->rx_info.up) {
				rx_refill(dev, GFP_ATOMIC);
				kick_rx(dev);
			}
		}

		if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
			schedule_task(&dev->tq_refill);
		else
			kick_rx(dev);
		if (dev->rx_info.idle)
			Dprintk("BAD\n");
	}

	if (unlikely(ISR_RXSOVR & isr)) {
		Dprintk("overrun: rxsovr\n");
		dev->stats.rx_over_errors ++;
	}
	if (unlikely(ISR_RXORN & isr)) {
		Dprintk("overrun: rxorn\n");
		dev->stats.rx_over_errors ++;
	}

	if ((ISR_RXRCMP & isr) && dev->rx_info.up)
		writel(CR_RXE, dev->base + CR);

	if (ISR_TXIDLE & isr) {
		u32 txdp;
		txdp = readl(dev->base + TXDP);
		dprintk("txdp: %08x\n", txdp);
		txdp -= dev->tx_phy_descs;
		dev->tx_idx = txdp / (DESC_SIZE * 4);
		if (dev->tx_idx >= NR_TX_DESC) {
			printk(KERN_ALERT "%s: BUG -- txdp out of range\n", dev->net_dev.name);
			dev->tx_idx = 0;
		}
		if (dev->tx_idx != dev->tx_free_idx)
			writel(CR_TXE, dev->base + CR);
			//kick_tx(dev);
		else
			dev->tx_idle = 1;
		mb();
		if (dev->tx_idx != dev->tx_free_idx)
			kick_tx(dev);
	}

	/* Defer tx ring processing until more than a minimum amount of
	 * work has accumulated
	 */
	if ((ISR_TXDESC | ISR_TXIDLE) & isr)
		do_tx_done(dev);

	if (ISR_MIB & isr) {
		spin_lock(&dev->misc_lock);
		ns83820_update_stats(dev);
		spin_unlock(&dev->misc_lock);
	}

	if (ISR_PHY & isr)
		phy_intr(dev);
	}

#if 0	/* Still working on the interrupt mitigation strategy */
	if (dev->ihr)
		writel(dev->ihr, dev->base + IHR);
#endif
}

static void ns83820_do_reset(struct ns83820 *dev, u32 which)
{
	Dprintk("resetting chip...\n");
	writel(which, dev->base + CR);
	do {
		schedule();
	} while (readl(dev->base + CR) & which);
	Dprintk("okay!\n");
}

static int ns83820_stop(struct net_device *_dev)
{
	struct ns83820 *dev = (struct ns83820 *)_dev;

	/* FIXME: protect against interrupt handler? */

	/* disable interrupts */
	writel(0, dev->base + IMR);
	writel(0, dev->base + IER);
	readl(dev->base + IER);

	dev->rx_info.up = 0;
	synchronize_irq();

	ns83820_do_reset(dev, CR_RST);

	synchronize_irq();

	dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
	ns83820_cleanup_rx(dev);
	ns83820_cleanup_tx(dev);

	return 0;
}

static int ns83820_open(struct net_device *_dev)
{
	struct ns83820 *dev = (struct ns83820 *)_dev;
	unsigned i;
	u32 desc;
	int ret;

	dprintk("ns83820_open\n");

	writel(0, dev->base + PQCR);

	ret = ns83820_setup_rx(dev);
	if (ret)
		goto failed;

	memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
	for (i=0; i<NR_TX_DESC; i++) {
		dev->tx_descs[(i * DESC_SIZE) + LINK]
				= cpu_to_le32(
				  dev->tx_phy_descs
				  + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
	}

	dev->tx_idx = 0;
	dev->tx_done_idx = 0;
	desc = dev->tx_phy_descs;
	writel(0, dev->base + TXDP_HI);
	writel(desc, dev->base + TXDP);

//printk("IMR: %08x / %08x\n", readl(dev->base + IMR), dev->IMR_cache);

	set_bit(0, &dev->tx_idle);
	netif_start_queue(&dev->net_dev);	/* FIXME: wait for phy to come up */

	return 0;

failed:
	ns83820_stop(_dev);
	return ret;
}

#if 0	/* FIXME: implement this! */
static void ns83820_tx_timeout(struct net_device *_dev)
{
	struct ns83820 *dev = (struct ns83820 *)_dev;

	printk("ns83820_tx_timeout\n");
}
#endif

static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
{
	unsigned i;
	for (i=0; i<3; i++) {
		u32 data;
#if 0	/* I've left this in as an example of how to use eeprom.h */
		data = eeprom_readw(&dev->ee, 0xa + 2 - i);
#else
		/* Read from the perfect match memory: this is loaded by
		 * the chip from the EEPROM via the EELOAD self test.
		 */
		writel(i*2, dev->base + RFCR);
		data = readl(dev->base + RFDR);
#endif
		*mac++ = data;
		*mac++ = data >> 8;
	}
}

static int ns83820_change_mtu(struct net_device *_dev, int new_mtu)
{
	if (new_mtu > RX_BUF_SIZE)
		return -EINVAL;
	_dev->mtu = new_mtu;
	return 0;
}

static void ns83820_set_multicast(struct net_device *_dev)
{
	struct ns83820 *dev = (void *)_dev;
	u8 *rfcr = dev->base + RFCR;
	u32 and_mask = 0xffffffff;
	u32 or_mask = 0;

	if (dev->net_dev.flags & IFF_PROMISC)
		or_mask |= RFCR_AAU | RFCR_AAM;
	else
		and_mask &= ~(RFCR_AAU | RFCR_AAM);

	if (dev->net_dev.flags & IFF_ALLMULTI)
		or_mask |= RFCR_AAM;
	else
		and_mask &= ~RFCR_AAM;

	spin_lock_irq(&dev->misc_lock);
	writel((readl(rfcr) & and_mask) | or_mask, rfcr);
	spin_unlock_irq(&dev->misc_lock);
}

static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
{
	struct ns83820 *dev;
	long addr;
	int err;

	dev = (struct ns83820 *)alloc_etherdev((sizeof *dev) - (sizeof dev->net_dev));
	err = -ENOMEM;
	if (!dev)
		goto out;

	spin_lock_init(&dev->rx_info.lock);
	spin_lock_init(&dev->tx_lock);
	spin_lock_init(&dev->misc_lock);
	dev->pci_dev = pci_dev;

	dev->ee.cache = &dev->MEAR_cache;
	dev->ee.lock = &dev->misc_lock;
	dev->net_dev.owner = THIS_MODULE;

	PREPARE_TQUEUE(&dev->tq_refill, queue_refill, dev);

	err = pci_enable_device(pci_dev);
	if (err) {
		printk(KERN_INFO "ns83820: pci_enable_dev: %d\n", err);
		goto out_free;
	}

	pci_set_master(pci_dev);
	addr = pci_resource_start(pci_dev, 1);
	dev->base = ioremap_nocache(addr, PAGE_SIZE);
	dev->tx_descs = pci_alloc_consistent(pci_dev,
			4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
	dev->rx_info.descs = pci_alloc_consistent(pci_dev,
			4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
	err = -ENOMEM;
	if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
		goto out_disable;

	dprintk("%p: %08lx  %p: %08lx\n", dev->tx_descs, dev->tx_phy_descs,
		dev->rx_info.descs, dev->rx_info.phy_descs);
	/* disable interrupts */
	writel(0, dev->base + IMR);
	writel(0, dev->base + IER);
	readl(dev->base + IER);

	dev->IMR_cache = 0;

	setup_ee_mem_bitbanger(&dev->ee, (long)dev->base + MEAR, 3, 2, 1, 0,
		0);

	err = request_irq(pci_dev->irq, ns83820_irq, SA_SHIRQ,
			  dev->net_dev.name, dev);
	if (err) {
		printk(KERN_INFO "ns83820: unable to register irq %d\n",
			pci_dev->irq);
		goto out_unmap;
	}

	if(register_netdev(&dev->net_dev)) goto out_unmap;

	dev->net_dev.open = ns83820_open;
	dev->net_dev.stop = ns83820_stop;
	dev->net_dev.hard_start_xmit = ns83820_hard_start_xmit;
	dev->net_dev.change_mtu = ns83820_change_mtu;
	dev->net_dev.get_stats = ns83820_get_stats;
	dev->net_dev.change_mtu = ns83820_change_mtu;
	dev->net_dev.set_multicast_list = ns83820_set_multicast;
	dev->net_dev.do_ioctl = ns83820_ioctl;
	//FIXME: dev->net_dev.tx_timeout = ns83820_tx_timeout;

	pci_set_drvdata(pci_dev, dev);

	ns83820_do_reset(dev, CR_RST);

	dprintk("start bist\n");
	writel(PTSCR_EEBIST_EN, dev->base + PTSCR);
	do {
		schedule();
	} while (readl(dev->base + PTSCR) & PTSCR_EEBIST_EN);
	dprintk("done bist\n");

	dprintk("start eeload\n");
	writel(PTSCR_EELOAD_EN, dev->base + PTSCR);
	do {
		schedule();
	} while (readl(dev->base + PTSCR) & PTSCR_EELOAD_EN);
	dprintk("done eeload\n");

	/* I love config registers */
	dev->CFG_cache = readl(dev->base + CFG);

	if ((dev->CFG_cache & CFG_PCI64_DET)) {
		printk("%s: enabling 64 bit PCI addressing.\n",
			dev->net_dev.name);
		dev->CFG_cache |= CFG_T64ADDR | CFG_DATA64_EN;
#if defined(USE_64BIT_ADDR)
		dev->net_dev.features |= NETIF_F_HIGHDMA;
#endif
	} else
		dev->CFG_cache &= ~(CFG_T64ADDR | CFG_DATA64_EN);

	dev->CFG_cache &= (CFG_TBI_EN  | CFG_MRM_DIS   | CFG_MWI_DIS |
			   CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
			   CFG_M64ADDR);
	dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
			  CFG_EXTSTS_EN   | CFG_EXD         | CFG_PESEL;
	dev->CFG_cache |= CFG_REQALG;
	dev->CFG_cache |= CFG_POW;
#ifdef USE_64BIT_ADDR
	dev->CFG_cache |= CFG_M64ADDR;
#endif
	/* Big endian mode does not seem to do what the docs suggest */
	dev->CFG_cache &= ~CFG_BEM;

	/* setup optical transceiver if we have one */
	if (dev->CFG_cache & CFG_TBI_EN) {
		printk("%s: enabling optical transceiver\n", dev->net_dev.name);
		writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);

		/* setup auto negotiation feature advertisement */
		writel(readl(dev->base + TANAR)
		       | TANAR_HALF_DUP | TANAR_FULL_DUP,
		       dev->base + TANAR);

		/* start auto negotiation */
		writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
		       dev->base + TBICR);
		writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
		dev->linkstate = LINK_AUTONEGOTIATE;

		dev->CFG_cache |= CFG_MODE_1000;
	}

	writel(dev->CFG_cache, dev->base + CFG);
	dprintk("CFG: %08x\n", dev->CFG_cache);

	if (readl(dev->base + SRR))
		writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);

	/* Note!  The DMA burst size interacts with packet
	 * transmission, such that the largest packet that
	 * can be transmitted is 8192 - FLTH - burst size.
	 * If only the transmit fifo was larger...
	 */
	writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA1024
		| ((1600 / 32) * 0x100),
		dev->base + TXCFG);

	/* Flush the interrupt holdoff timer */
	writel(0x000, dev->base + IHR);
	writel(0x100, dev->base + IHR);

	/* Set Rx to full duplex, don't accept runt, errored, long or length
	 * range errored packets.  Set MXDMA to 7 => 512 word burst
	 */
	writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
		| RXCFG_ALP
		| RXCFG_MXDMA | 0, dev->base + RXCFG);

	/* Disable priority queueing */
	writel(0, dev->base + PQCR);

	/* Enable IP checksum validation and detetion of VLAN headers.
	 * Note: do not set the reject options as at least the 0x102
	 * revision of the chip does not properly accept IP fragments
	 * at least for UDP.
	 */
	writel(VRCR_IPEN | VRCR_VTDEN, dev->base + VRCR);

	/* Enable per-packet TCP/UDP/IP checksumming */
	writel(VTCR_PPCHK, dev->base + VTCR);

	/* Disable Pause frames */
	writel(0, dev->base + PCR);

	/* Disable Wake On Lan */
	writel(0, dev->base + WCSR);

	ns83820_getmac(dev, dev->net_dev.dev_addr);

	/* Yes, we support dumb IP checksum on transmit */
	dev->net_dev.features |= NETIF_F_SG;
	dev->net_dev.features |= NETIF_F_IP_CSUM;
#if defined(USE_64BIT_ADDR) || defined(CONFIG_HIGHMEM4G)
	dev->net_dev.features |= NETIF_F_HIGHDMA;
#endif

	printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
		dev->net_dev.name,
		(unsigned)readl(dev->base + SRR) >> 8,
		(unsigned)readl(dev->base + SRR) & 0xff,
		dev->net_dev.dev_addr[0], dev->net_dev.dev_addr[1],
		dev->net_dev.dev_addr[2], dev->net_dev.dev_addr[3],
		dev->net_dev.dev_addr[4], dev->net_dev.dev_addr[5],
		addr, pci_dev->irq,
		(dev->net_dev.features & NETIF_F_HIGHDMA) ? "sg" : "h,sg"
		);

	return 0;

out_unmap:
	iounmap(dev->base);
out_disable:
	pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
	pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
	pci_disable_device(pci_dev);
out_free:
	kfree(dev);
	pci_set_drvdata(pci_dev, NULL);
out:
	return err;
}

static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
{
	struct ns83820	*dev = pci_get_drvdata(pci_dev);

	if (!dev)			/* paranoia */
		return;

	writel(0, dev->base + IMR);	/* paranoia */
	writel(0, dev->base + IER);
	readl(dev->base + IER);

	unregister_netdev(&dev->net_dev);
	free_irq(dev->pci_dev->irq, dev);
	iounmap(dev->base);
	pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
			dev->tx_descs, dev->tx_phy_descs);
	pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
			dev->rx_info.descs, dev->rx_info.phy_descs);
	pci_disable_device(dev->pci_dev);
	kfree(dev);
	pci_set_drvdata(pci_dev, NULL);
}

static struct pci_device_id ns83820_pci_tbl[] __devinitdata = {
	{ 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
	{ 0, },
};

static struct pci_driver driver = {
	name:		"ns83820",
	id_table:	ns83820_pci_tbl,
	probe:		ns83820_init_one,
	remove:		__devexit_p(ns83820_remove_one),
#if 0	/* FIXME: implement */
	suspend:	,
	resume:		,
#endif
};


static int __init ns83820_init(void)
{
	printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
	return pci_module_init(&driver);
}

static void __exit ns83820_exit(void)
{
	pci_unregister_driver(&driver);
}

MODULE_AUTHOR("Benjamin LaHaise <[e-mail]>");
MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
MODULE_LICENSE("GPL");

MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);

module_init(ns83820_init);
module_exit(ns83820_exit);