hp100.h

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 * (Page HW_MAP, EARLYTXCFG, Offset 0x16)
 */
#define HP100_EN_EARLY_TX       0x8000	/* 1=Enable Early TX */
#define HP100_EN_ADAPTIVE       0x4000	/* 1=Enable adaptive mode */
#define HP100_EN_TX_UR_IRQ      0x2000	/* reserved, must be 0 */
#define HP100_EN_LOW_TX         0x1000	/* reserved, must be 0 */
#define HP100_ET_CNT_MASK       0x0fff	/* bits 11..0: ET counters */

/*
 * Early RX Configuration and Control Register
 * (Page HW_MAP, EARLYRXCFG, Offset 0x18)
 */
#define HP100_EN_EARLY_RX       0x80	/* 1=Enable Early RX */
#define HP100_EN_LOW_RX         0x40	/* reserved, must be 0 */
#define HP100_RX_TRIP_MASK      0x1f	/* bits 4..0: threshold at which the
					 * early rx circuit will start the
					 * dma of received packet into system
					 * memory for BM */

/*
 *  Serial Devices Control Register
 * (Page EEPROM_CTRL, EEPROM_CTRL, Offset 0x08)
 */
#define HP100_EEPROM_LOAD	0x0001	/* 0->1 loads EEPROM into registers. */
					/* When it goes back to 0, load is   */
					/* complete. This should take ~600us. */

/*
 * 10MB LAN Control and Configuration Register I
 * (Page MAC_CTRL, 10_LAN_CFG_1, Offset 0x08)
 */
#define HP100_MAC10_SEL		0xc0	/* Get bits to indicate MAC */
#define HP100_AUI_SEL		0x20	/* Status of AUI selection */
#define HP100_LOW_TH		0x10	/* 0:No, 1:Yes allow better cabling */
#define HP100_LINK_BEAT_DIS	0x08	/* 0:Enable, 1:Disable link beat */
#define HP100_LINK_BEAT_ST	0x04	/* 0:No, 1:Yes link beat being Rx */
#define HP100_R_ROL_ST		0x02	/* 0:No, 1:Yes Rx twisted pair has */
					/*             been reversed */
#define HP100_AUI_ST		0x01	/* 0:No, 1:Yes use AUI on TP card */

/*
 * 10 MB LAN Control and Configuration Register II
 * (Page MAC_CTRL, 10_LAN_CFG_2, Offset 0x09)
 */
#define HP100_SQU_ST		0x01	/* 0:No, 1:Yes collision signal sent */
					/*       after Tx.Only used for AUI. */
#define HP100_FULLDUP           0x02	/* 1: LXT901 XCVR fullduplx enabled */
#define HP100_DOT3_MAC          0x04	/* 1: DOT 3 Mac sel. unless Autosel */

/*
 * MAC Selection, use with MAC10_SEL bits
 */
#define HP100_AUTO_SEL_10	0x0	/* Auto select */
#define HP100_XCVR_LXT901_10	0x1	/* LXT901 10BaseT transceiver */
#define HP100_XCVR_7213		0x2	/* 7213 transceiver */
#define HP100_XCVR_82503	0x3	/* 82503 transceiver */

/*
 *  100MB LAN Training Register
 * (Page MAC_CTRL, VG_LAN_CFG_2, Offset 0x0b) (old, pre 802.12)
 */
#define HP100_FRAME_FORMAT	0x08	/* 0:802.3, 1:802.5 frames */
#define HP100_BRIDGE		0x04	/* 0:No, 1:Yes tell hub i am a bridge */
#define HP100_PROM_MODE		0x02	/* 0:No, 1:Yes tell hub card is */
					/*         promiscuous */
#define HP100_REPEATER		0x01	/* 0:No, 1:Yes tell hub MAC wants to */
					/*         be a cascaded repeater */

/*
 * 100MB LAN Control and Configuration Register
 * (Page MAC_CTRL, VG_LAN_CFG_1, Offset 0x0a) 
 */
#define HP100_VG_SEL	        0x80	/* 0:No, 1:Yes use 100 Mbit MAC */
#define HP100_LINK_UP_ST	0x40	/* 0:No, 1:Yes endnode logged in */
#define HP100_LINK_CABLE_ST	0x20	/* 0:No, 1:Yes cable can hear tones */
					/*         from  hub */
#define HP100_LOAD_ADDR		0x10	/* 0->1 card addr will be sent  */
					/* 100ms later the link status  */
					/* bits are valid */
#define HP100_LINK_CMD		0x08	/* 0->1 link will attempt to log in. */
					/* 100ms later the link status */
					/* bits are valid */
#define HP100_TRN_DONE          0x04	/* NEW ETR-Chips only: Will be reset */
					/* after LinkUp Cmd is given and set */
					/* when training has completed. */
#define HP100_LINK_GOOD_ST	0x02	/* 0:No, 1:Yes cable passed training */
#define HP100_VG_RESET		0x01	/* 0:Yes, 1:No reset the 100VG MAC */


/*
 *  MAC Configuration Register I
 * (Page MAC_CTRL, MAC_CFG_1, Offset 0x0c)
 */
#define HP100_RX_IDLE		0x80	/* 0:Yes, 1:No currently receiving pkts */
#define HP100_TX_IDLE		0x40	/* 0:Yes, 1:No currently Txing pkts */
#define HP100_RX_EN		0x20	/* 1: allow receiving of pkts */
#define HP100_TX_EN		0x10	/* 1: allow transmitting of pkts */
#define HP100_ACC_ERRORED	0x08	/* 0:No, 1:Yes allow Rx of errored pkts */
#define HP100_ACC_MC		0x04	/* 0:No, 1:Yes allow Rx of multicast pkts */
#define HP100_ACC_BC		0x02	/* 0:No, 1:Yes allow Rx of broadcast pkts */
#define HP100_ACC_PHY		0x01	/* 0:No, 1:Yes allow Rx of ALL phys. pkts */
#define HP100_MAC1MODEMASK	0xf0	/* Hide ACC bits */
#define HP100_MAC1MODE1		0x00	/* Receive nothing, must also disable RX */
#define HP100_MAC1MODE2		0x00
#define HP100_MAC1MODE3		HP100_MAC1MODE2 | HP100_ACC_BC
#define HP100_MAC1MODE4		HP100_MAC1MODE3 | HP100_ACC_MC
#define HP100_MAC1MODE5		HP100_MAC1MODE4	/* set mc hash to all ones also */
#define HP100_MAC1MODE6		HP100_MAC1MODE5 | HP100_ACC_PHY	/* Promiscuous */
/* Note MODE6 will receive all GOOD packets on the LAN. This really needs
   a mode 7 defined to be LAN Analyzer mode, which will receive errored and
   runt packets, and keep the CRC bytes. */
#define HP100_MAC1MODE7		HP100_MAC1MODE6 | HP100_ACC_ERRORED

/*
 *  MAC Configuration Register II 
 * (Page MAC_CTRL, MAC_CFG_2, Offset 0x0d)
 */
#define HP100_TR_MODE		0x80	/* 0:No, 1:Yes support Token Ring formats */
#define HP100_TX_SAME		0x40	/* 0:No, 1:Yes Tx same packet continuous */
#define HP100_LBK_XCVR		0x20	/* 0:No, 1:Yes loopback through MAC & */
					/*   transceiver */
#define HP100_LBK_MAC		0x10	/* 0:No, 1:Yes loopback through MAC */
#define HP100_CRC_I		0x08	/* 0:No, 1:Yes inhibit CRC on Tx packets */
#define HP100_ACCNA             0x04	/* 1: For 802.5: Accept only token ring
					 * group addr that maches NA mask */
#define HP100_KEEP_CRC		0x02	/* 0:No, 1:Yes keep CRC on Rx packets. */
					/*   The length will reflect this. */
#define HP100_ACCFA             0x01	/* 1: For 802.5: Accept only functional
					 * addrs that match FA mask (page1) */
#define HP100_MAC2MODEMASK	0x02
#define HP100_MAC2MODE1		0x00
#define HP100_MAC2MODE2		0x00
#define HP100_MAC2MODE3		0x00
#define HP100_MAC2MODE4		0x00
#define HP100_MAC2MODE5		0x00
#define HP100_MAC2MODE6		0x00
#define HP100_MAC2MODE7		KEEP_CRC

/*
 * MAC Configuration Register III 
 * (Page MAC_CTRL, MAC_CFG_3, Offset 0x0e) 
 */
#define HP100_PACKET_PACE       0x03	/* Packet Pacing:
					 * 00: No packet pacing
					 * 01: 8 to 16 uS delay
					 * 10: 16 to 32 uS delay
					 * 11: 32 to 64 uS delay
					 */
#define HP100_LRF_EN            0x04	/* 1: External LAN Rcv Filter and
					 * TCP/IP Checksumming enabled. */
#define HP100_AUTO_MODE         0x10	/* 1: AutoSelect between 10/100 */

/*
 * MAC Configuration Register IV 
 * (Page MAC_CTRL, MAC_CFG_4, Offset 0x0f)
 */
#define HP100_MAC_SEL_ST        0x01	/* (R): Status of external VGSEL
					 * Signal, 1=100VG, 0=10Mbit sel. */
#define HP100_LINK_FAIL_ST      0x02	/* (R): Status of Link Fail portion
					 * of the Misc. Interrupt */

/* 
 *  100 MB LAN Training Request/Allowed Registers 
 * (Page MAC_CTRL, TRAIN_REQUEST and TRAIN_ALLOW, Offset 0x14-0x16)(ETR parts only)
 */
#define HP100_MACRQ_REPEATER         0x0001	/* 1: MAC tells HUB it wants to be 
						 *    a cascaded repeater
						 * 0: ... wants to be a DTE */
#define HP100_MACRQ_PROMSC           0x0006	/* 2 bits: Promiscious mode
						 * 00: Rcv only unicast packets
						 *     specifically addr to this
						 *     endnode
						 * 10: Rcv all pckts fwded by 
						 *     the local repeater */
#define HP100_MACRQ_FRAMEFMT_EITHER  0x0018	/* 11: either format allowed */
#define HP100_MACRQ_FRAMEFMT_802_3   0x0000	/* 00: 802.3 is requested */
#define HP100_MACRQ_FRAMEFMT_802_5   0x0010	/* 10: 802.5 format is requested */
#define HP100_CARD_MACVER            0xe000	/* R: 3 bit Cards 100VG MAC version */
#define HP100_MALLOW_REPEATER        0x0001	/* If reset, requested access as an
						 * end node is allowed */
#define HP100_MALLOW_PROMSC          0x0004	/* 2 bits: Promiscious mode
						 * 00: Rcv only unicast packets
						 *     specifically addr to this
						 *     endnode
						 * 10: Rcv all pckts fwded by 
						 *     the local repeater */
#define HP100_MALLOW_FRAMEFMT        0x00e0	/* 2 bits: Frame Format
						 * 00: 802.3 format will be used
						 * 10: 802.5 format will be used */
#define HP100_MALLOW_ACCDENIED       0x0400	/* N bit */
#define HP100_MALLOW_CONFIGURE       0x0f00	/* C bit */
#define HP100_MALLOW_DUPADDR         0x1000	/* D bit */
#define HP100_HUB_MACVER             0xe000	/* R: 3 bit 802.12 MAC/RMAC training */
					     /*    protocol of repeater */

/* ****************************************************************************** */

/*
 *  Set/Reset bits
 */
#define HP100_SET_HB		0x0100	/* 0:Set fields to 0 whose mask is 1 */
#define HP100_SET_LB		0x0001	/* HB sets upper byte, LB sets lower byte */
#define HP100_RESET_HB		0x0000	/* For readability when resetting bits */
#define HP100_RESET_LB		0x0000	/* For readability when resetting bits */

/*
 *  Misc. Constants
 */
#define HP100_LAN_100		100	/* lan_type value for VG */
#define HP100_LAN_10		10	/* lan_type value for 10BaseT */
#define HP100_LAN_ERR		(-1)	/* lan_type value for link down */

#define TRUE 1
#define FALSE 0


/* 
 * Bus Master Data Structures  ----------------------------------------------
 */

#define MAX_RX_PDL              30	/* Card limit = 31 */
#define MAX_RX_FRAG             2	/* Don't need more... */
#define MAX_TX_PDL              29
#define MAX_TX_FRAG             2	/* Limit = 31 */

/* Define total PDL area size in bytes (should be 4096) */
/* This is the size of kernel (dma) memory that will be allocated. */
#define MAX_RINGSIZE ((MAX_RX_FRAG*8+4+4)*MAX_RX_PDL+(MAX_TX_FRAG*8+4+4)*MAX_TX_PDL)+16

/* Ethernet Packet Sizes */
#define MIN_ETHER_SIZE          60
#define MAX_ETHER_SIZE          1514	/* Needed for preallocation of */
					/* skb buffer when busmastering */

/* Tx or Rx Ring Entry */
typedef struct hp100_ring {
	u_int *pdl;		/* Address of PDLs PDH, dword before
				 * this address is used for rx hdr */
	u_int pdl_paddr;	/* Physical address of PDL */
	struct sk_buff *skb;
	struct hp100_ring *next;
} hp100_ring_t;



/* Mask for Header Descriptor */
#define HP100_PKT_LEN_MASK	0x1FFF	/* AND with RxLength to get length */


/* Receive Packet Status.  Note, the error bits are only valid if ACC_ERRORED 
   bit in the MAC Configuration Register 1 is set. */
#define HP100_RX_PRI		0x8000	/* 0:No, 1:Yes packet is priority */
#define HP100_SDF_ERR		0x4000	/* 0:No, 1:Yes start of frame error */
#define HP100_SKEW_ERR		0x2000	/* 0:No, 1:Yes skew out of range */
#define HP100_BAD_SYMBOL_ERR	0x1000	/* 0:No, 1:Yes invalid symbol received */
#define HP100_RCV_IPM_ERR	0x0800	/* 0:No, 1:Yes pkt had an invalid packet */
					/*   marker */
#define HP100_SYMBOL_BAL_ERR	0x0400	/* 0:No, 1:Yes symbol balance error */
#define HP100_VG_ALN_ERR	0x0200	/* 0:No, 1:Yes non-octet received */
#define HP100_TRUNC_ERR		0x0100	/* 0:No, 1:Yes the packet was truncated */
#define HP100_RUNT_ERR		0x0040	/* 0:No, 1:Yes pkt length < Min Pkt */
					/*   Length Reg. */
#define HP100_ALN_ERR		0x0010	/* 0:No, 1:Yes align error. */
#define HP100_CRC_ERR		0x0008	/* 0:No, 1:Yes CRC occurred. */

/* The last three bits indicate the type of destination address */

#define HP100_MULTI_ADDR_HASH	0x0006	/* 110: Addr multicast, matched hash */
#define HP100_BROADCAST_ADDR	0x0003	/* x11: Addr broadcast */
#define HP100_MULTI_ADDR_NO_HASH 0x0002	/* 010: Addr multicast, didn't match hash */
#define HP100_PHYS_ADDR_MATCH	0x0001	/* x01: Addr was physical and mine */
#define HP100_PHYS_ADDR_NO_MATCH 0x0000	/* x00: Addr was physical but not mine */

/*
 *  macros
 */

#define hp100_inb( reg ) \
        inb( ioaddr + HP100_REG_##reg )
#define hp100_inw( reg ) \
	inw( ioaddr + HP100_REG_##reg )
#define hp100_inl( reg ) \
	inl( ioaddr + HP100_REG_##reg )
#define hp100_outb( data, reg ) \
	outb( data, ioaddr + HP100_REG_##reg )
#define hp100_outw( data, reg ) \
	outw( data, ioaddr + HP100_REG_##reg )
#define hp100_outl( data, reg ) \
	outl( data, ioaddr + HP100_REG_##reg )
#define hp100_orb( data, reg ) \
	outb( inb( ioaddr + HP100_REG_##reg ) | (data), ioaddr + HP100_REG_##reg )
#define hp100_orw( data, reg ) \
	outw( inw( ioaddr + HP100_REG_##reg ) | (data), ioaddr + HP100_REG_##reg )
#define hp100_andb( data, reg ) \
	outb( inb( ioaddr + HP100_REG_##reg ) & (data), ioaddr + HP100_REG_##reg )
#define hp100_andw( data, reg ) \
	outw( inw( ioaddr + HP100_REG_##reg ) & (data), ioaddr + HP100_REG_##reg )

#define hp100_page( page ) \
	outw( HP100_PAGE_##page, ioaddr + HP100_REG_PAGING )
#define hp100_ints_off() \
	outw( HP100_INT_EN | HP100_RESET_LB, ioaddr + HP100_REG_OPTION_LSW )
#define hp100_ints_on() \
	outw( HP100_INT_EN | HP100_SET_LB, ioaddr + HP100_REG_OPTION_LSW )
#define hp100_mem_map_enable() \
	outw( HP100_MMAP_DIS | HP100_RESET_HB, ioaddr + HP100_REG_OPTION_LSW )
#define hp100_mem_map_disable() \
	outw( HP100_MMAP_DIS | HP100_SET_HB, ioaddr + HP100_REG_OPTION_LSW )