fore200e.h

linux和2410结合开发 用他可以生成2410所需的zImage文件

	u32         reg    : 8,    /* register index                      */
	u32         value  : 8,    /* register value                      */
	u32         mask   : 8     /* register mask that specifies which
				      bits of the register value field
				      are significant                     */
    )
} oc3_opcode_t;


/* set/get OC-3 regs command block */

typedef struct oc3_block {
    struct oc3_opcode opcode;        /* set/get OC-3 regs command opcode     */
    u32               regs_haddr;    /* host DMA address of OC-3 regs buffer */
} oc3_block_t;


/* physical encoding statistics */

typedef struct stats_phy {
    u32 crc_header_errors;    /* cells received with bad header CRC */
    u32 framing_errors;       /* cells received with bad framing    */
    u32 pad[ 2 ];             /* i960 padding                       */
} stats_phy_t;


/* OC-3 statistics */

typedef struct stats_oc3 {
    u32 section_bip8_errors;    /* section 8 bit interleaved parity    */
    u32 path_bip8_errors;       /* path 8 bit interleaved parity       */
    u32 line_bip24_errors;      /* line 24 bit interleaved parity      */
    u32 line_febe_errors;       /* line far end block errors           */
    u32 path_febe_errors;       /* path far end block errors           */
    u32 corr_hcs_errors;        /* correctable header check sequence   */
    u32 ucorr_hcs_errors;       /* uncorrectable header check sequence */
    u32 pad[ 1 ];               /* i960 padding                        */
} stats_oc3_t;


/* ATM statistics */

typedef struct stats_atm {
    u32	cells_transmitted;    /* cells transmitted                 */
    u32	cells_received;       /* cells received                    */
    u32	vpi_bad_range;        /* cell drops: VPI out of range      */
    u32	vpi_no_conn;          /* cell drops: no connection for VPI */
    u32	vci_bad_range;        /* cell drops: VCI out of range      */
    u32	vci_no_conn;          /* cell drops: no connection for VCI */
    u32	pad[ 2 ];             /* i960 padding                      */
} stats_atm_t;

/* AAL0 statistics */

typedef struct stats_aal0 {
    u32	cells_transmitted;    /* cells transmitted */
    u32	cells_received;       /* cells received    */
    u32	cells_dropped;        /* cells dropped     */
    u32	pad[ 1 ];             /* i960 padding      */
} stats_aal0_t;


/* AAL3/4 statistics */

typedef struct stats_aal34 {
    u32	cells_transmitted;         /* cells transmitted from segmented PDUs */
    u32	cells_received;            /* cells reassembled into PDUs           */
    u32	cells_crc_errors;          /* payload CRC error count               */
    u32	cells_protocol_errors;     /* SAR or CS layer protocol errors       */
    u32	cells_dropped;             /* cells dropped: partial reassembly     */
    u32	cspdus_transmitted;        /* CS PDUs transmitted                   */
    u32	cspdus_received;           /* CS PDUs received                      */
    u32	cspdus_protocol_errors;    /* CS layer protocol errors              */
    u32	cspdus_dropped;            /* reassembled PDUs drop'd (in cells)    */
    u32	pad[ 3 ];                  /* i960 padding                          */
} stats_aal34_t;


/* AAL5 statistics */

typedef struct stats_aal5 {
    u32	cells_transmitted;         /* cells transmitted from segmented SDUs */
    u32	cells_received;		   /* cells reassembled into SDUs           */
    u32	cells_dropped;		   /* reassembled PDUs dropped (in cells)   */
    u32	congestion_experienced;    /* CRC error and length wrong            */
    u32	cspdus_transmitted;        /* CS PDUs transmitted                   */
    u32	cspdus_received;           /* CS PDUs received                      */
    u32	cspdus_crc_errors;         /* CS PDUs CRC errors                    */
    u32	cspdus_protocol_errors;    /* CS layer protocol errors              */
    u32	cspdus_dropped;            /* reassembled PDUs dropped              */
    u32	pad[ 3 ];                  /* i960 padding                          */
} stats_aal5_t;


/* auxiliary statistics */

typedef struct stats_aux {
    u32	small_b1_failed;     /* receive BD allocation failures  */
    u32	large_b1_failed;     /* receive BD allocation failures  */
    u32	small_b2_failed;     /* receive BD allocation failures  */
    u32	large_b2_failed;     /* receive BD allocation failures  */
    u32	rpd_alloc_failed;    /* receive PDU allocation failures */
    u32	receive_carrier;     /* no carrier = 0, carrier = 1     */
    u32	pad[ 2 ];            /* i960 padding                    */
} stats_aux_t;


/* whole statistics buffer */

typedef struct stats {
    struct stats_phy   phy;      /* physical encoding statistics */
    struct stats_oc3   oc3;      /* OC-3 statistics              */
    struct stats_atm   atm;      /* ATM statistics               */
    struct stats_aal0  aal0;     /* AAL0 statistics              */
    struct stats_aal34 aal34;    /* AAL3/4 statistics            */
    struct stats_aal5  aal5;     /* AAL5 statistics              */
    struct stats_aux   aux;      /* auxiliary statistics         */
} stats_t;


/* get statistics command opcode */

typedef struct stats_opcode {
    BITFIELD2(
        enum opcode opcode :  8,    /* cp opcode */
        u32         pad    : 24     /* reserved  */
    )
} stats_opcode_t;


/* get statistics command block */

typedef struct stats_block {
    struct stats_opcode opcode;         /* get statistics command opcode    */
    u32                 stats_haddr;    /* host DMA address of stats buffer */
} stats_block_t;


/* expansion PROM data (PCI specific) */

typedef struct prom_data {
    u32 hw_revision;      /* hardware revision   */
    u32 serial_number;    /* board serial number */
    u8  mac_addr[ 8 ];    /* board MAC address   */
} prom_data_t;


/* get expansion PROM data command opcode */

typedef struct prom_opcode {
    BITFIELD2(
        enum opcode opcode :  8,    /* cp opcode */
        u32         pad    : 24     /* reserved  */
    )
} prom_opcode_t;


/* get expansion PROM data command block */

typedef struct prom_block {
    struct prom_opcode opcode;        /* get PROM data command opcode    */
    u32                prom_haddr;    /* host DMA address of PROM buffer */
} prom_block_t;


/* cp command */

typedef union cmd {
    enum   opcode           opcode;           /* operation code          */
    struct activate_block   activate_block;   /* activate VC             */
    struct deactivate_block deactivate_block; /* deactivate VC           */
    struct stats_block      stats_block;      /* get statistics          */
    struct prom_block       prom_block;       /* get expansion PROM data */
    struct oc3_block        oc3_block;        /* get/set OC-3 registers  */
    u32                     pad[ 4 ];         /* i960 padding            */
} cmd_t;


/* cp resident command queue */

typedef struct cp_cmdq_entry {
    union cmd cmd;             /* command                               */
    u32       status_haddr;    /* host DMA address of completion status */
    u32       pad[ 3 ];        /* i960 padding                          */
} cp_cmdq_entry_t;


/* host resident transmit queue entry */

typedef struct host_txq_entry {
    struct cp_txq_entry*   cp_entry;    /* addr of cp resident tx queue entry */
    enum   status*         status;      /* addr of host resident status       */
    struct tpd*            tpd;         /* addr of transmit PDU descriptor    */
    u32                    tpd_dma;     /* DMA address of tpd                 */
    struct sk_buff*        skb;         /* related skb                        */
    struct atm_vcc*        vcc;         /* related vcc                        */
    void*                  data;        /* copy of misaligned data            */
} host_txq_entry_t;


/* host resident receive queue entry */

typedef struct host_rxq_entry {
    struct cp_rxq_entry* cp_entry;    /* addr of cp resident rx queue entry */
    enum   status*       status;      /* addr of host resident status       */
    struct rpd*          rpd;         /* addr of receive PDU descriptor     */
    u32                  rpd_dma;     /* DMA address of rpd                 */
} host_rxq_entry_t;


/* host resident buffer supply queue entry */

typedef struct host_bsq_entry {
    struct cp_bsq_entry* cp_entry;         /* addr of cp resident buffer supply queue entry */
    enum   status*       status;           /* addr of host resident status                  */
    struct rbd_block*    rbd_block;        /* addr of receive buffer descriptor block       */
    u32                  rbd_block_dma;    /* DMA address od rdb                            */
} host_bsq_entry_t;


/* host resident command queue entry */

typedef struct host_cmdq_entry {
    struct cp_cmdq_entry* cp_entry;    /* addr of cp resident cmd queue entry */
    enum   status*        status;      /* addr of host resident status        */
} host_cmdq_entry_t;


/* chunk of memory */

typedef struct chunk {
    void* alloc_addr;    /* base address of allocated chunk */
    void* align_addr;    /* base address of aligned chunk   */
    u32   dma_addr;      /* DMA address of aligned chunk    */
    int   direction;     /* direction of DMA mapping        */
    u32   alloc_size;    /* length of allocated chunk       */
    u32   align_size;    /* length of aligned chunk         */
} chunk_t;

#define dma_size align_size             /* DMA useable size */


/* host resident receive buffer */

typedef struct buffer {
    struct buffer*       next;        /* next receive buffer     */
    enum   buffer_scheme scheme;      /* buffer scheme           */
    enum   buffer_magn   magn;        /* buffer magnitude        */
    struct chunk         data;        /* data buffer             */
} buffer_t;


#if (BITS_PER_LONG == 32)
#define FORE200E_BUF2HDL(buffer)    ((u32)(buffer))
#define FORE200E_HDL2BUF(handle)    ((struct buffer*)(handle))
#else   /* deal with 64 bit pointers */
#define FORE200E_BUF2HDL(buffer)    ((u32)((u64)(buffer)))
#define FORE200E_HDL2BUF(handle)    ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET))
#endif


/* host resident command queue */

typedef struct host_cmdq {
    struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ];    /* host resident cmd queue entries        */
    int                    head;                            /* head of cmd queue                      */
    struct chunk           status;                          /* array of completion status      */
} host_cmdq_t;


/* host resident transmit queue */

typedef struct host_txq {
    struct host_txq_entry host_entry[ QUEUE_SIZE_TX ];    /* host resident tx queue entries         */
    int                   head;                           /* head of tx queue                       */
    struct chunk          tpd;                            /* array of tpds                          */
    struct chunk          status;                         /* arry of completion status              */
    int                   txing;                          /* number of pending PDUs in tx queue     */
} host_txq_t;


/* host resident receive queue */

typedef struct host_rxq {
    struct host_rxq_entry  host_entry[ QUEUE_SIZE_RX ];    /* host resident rx queue entries         */
    int                    head;                           /* head of rx queue                       */
    struct chunk           rpd;                            /* array of rpds                          */
    struct chunk           status;                         /* array of completion status             */
} host_rxq_t;


/* host resident buffer supply queues */

typedef struct host_bsq {
    struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ];    /* host resident buffer supply queue entries */
    int                   head;                           /* head of buffer supply queue               */
    struct chunk          rbd_block;                      /* array of rbds                             */
    struct chunk          status;                         /* array of completion status                */
    struct buffer*        buffer;                         /* array of rx buffers                       */
    int                   free;                           /* index of first free rx buffer             */
    volatile int          count;                          /* count of supplied rx buffers              */
} host_bsq_t;


/* header of the firmware image */

typedef struct fw_header {
    u32 magic;           /* magic number                               */
    u32 version;         /* firware version id                         */
    u32 load_offset;     /* fw load offset in board memory             */
    u32 start_offset;    /* fw execution start address in board memory */
} fw_header_t;

#define FW_HEADER_MAGIC  0x65726f66    /* 'fore' */


/* receive buffer supply queues scheme specification */

typedef struct bs_spec {
    u32	queue_length;      /* queue capacity                     */
    u32	buffer_size;	   /* host buffer size			 */
    u32	pool_size;	   /* number of rbds			 */
    u32	supply_blksize;    /* num of rbds in I/O block (multiple
			      of 4 between 4 and 124 inclusive)	 */
} bs_spec_t;


/* initialization command block (one-time command, not in cmd queue) */