idt77252.h

linux和2410结合开发 用他可以生成2410所需的zImage文件

#define SAR_CFG_RSVD2          0x00000200  /* Reserved                       */
#define SAR_CFG_CACHE          0x00000100  /* DMA on Cache Line Boundary     */
#define SAR_CFG_TMOIE          0x00000080  /* Timer Roll Over Int Enable     */
#define SAR_CFG_FBIE           0x00000040  /* Free Buffer Queue Int Enable   */
#define SAR_CFG_TXEN           0x00000020  /* Transmit Operation Enable      */
#define SAR_CFG_TXINT          0x00000010  /* Transmit status Int Enable     */
#define SAR_CFG_TXUIE          0x00000008  /* Transmit underrun Int Enable   */
#define SAR_CFG_UMODE          0x00000004  /* Utopia Mode Select             */
#define SAR_CFG_TXSFI          0x00000002  /* Transmit status Full Int Enable*/
#define SAR_CFG_PHYIE          0x00000001  /* PHY Interrupt Enable           */

#define SAR_CFG_TX_FIFO_SIZE_MASK 0x0C000000  /* TX FIFO Size Mask           */
#define SAR_CFG_RXSTQSIZE_MASK 0x00C00000
#define SAR_CFG_CNTBL_MASK     0x00030000
#define SAR_CFG_RXINT_MASK     0x00007000


/*****************************************************************************/
/*                                                                           */
/*   Status Register bits                                                    */
/*                                                                           */
/*****************************************************************************/

#define SAR_STAT_FRAC_3     0xF0000000 /* Fraction of Free Buffer Queue 3 */
#define SAR_STAT_FRAC_2     0x0F000000 /* Fraction of Free Buffer Queue 2 */
#define SAR_STAT_FRAC_1     0x00F00000 /* Fraction of Free Buffer Queue 1 */
#define SAR_STAT_FRAC_0     0x000F0000 /* Fraction of Free Buffer Queue 0 */
#define SAR_STAT_TSIF       0x00008000 /* Transmit Status Indicator       */
#define SAR_STAT_TXICP      0x00004000 /* Transmit Status Indicator       */
#define SAR_STAT_RSVD1      0x00002000 /* Reserved                        */
#define SAR_STAT_TSQF       0x00001000 /* Transmit Status Queue full      */
#define SAR_STAT_TMROF      0x00000800 /* Timer overflow                  */
#define SAR_STAT_PHYI       0x00000400 /* PHY device Interrupt flag       */
#define SAR_STAT_CMDBZ      0x00000200 /* ABR SAR Comand Busy Flag        */
#define SAR_STAT_FBQ3A      0x00000100 /* Free Buffer Queue 3 Attention   */
#define SAR_STAT_FBQ2A      0x00000080 /* Free Buffer Queue 2 Attention   */
#define SAR_STAT_RSQF       0x00000040 /* Receive Status Queue full       */
#define SAR_STAT_EPDU       0x00000020 /* End Of PDU Flag                 */
#define SAR_STAT_RAWCF      0x00000010 /* Raw Cell Flag                   */ 
#define SAR_STAT_FBQ1A      0x00000008 /* Free Buffer Queue 1 Attention   */
#define SAR_STAT_FBQ0A      0x00000004 /* Free Buffer Queue 0 Attention   */
#define SAR_STAT_RSQAF      0x00000002 /* Receive Status Queue almost full*/  
#define SAR_STAT_RSVD2      0x00000001 /* Reserved                        */


/*****************************************************************************/
/*                                                                           */
/*   General Purpose Register bits                                           */
/*                                                                           */
/*****************************************************************************/

#define SAR_GP_TXNCC_MASK   0xff000000  /* Transmit Negative Credit Count   */
#define SAR_GP_EEDI         0x00010000  /* EEPROM Data In                   */
#define SAR_GP_BIGE         0x00008000  /* Big Endian Operation             */
#define SAR_GP_RM_NORMAL    0x00000000  /* Normal handling of RM cells      */
#define SAR_GP_RM_TO_RCQ    0x00002000  /* put RM cells into Raw Cell Queue */
#define SAR_GP_RM_RSVD      0x00004000  /* Reserved                         */
#define SAR_GP_RM_INHIBIT   0x00006000  /* Inhibit update of Connection tab */
#define SAR_GP_PHY_RESET    0x00000008  /* PHY Reset                        */
#define SAR_GP_EESCLK	    0x00000004	/* EEPROM SCLK			    */
#define SAR_GP_EECS	    0x00000002	/* EEPROM Chip Select		    */
#define SAR_GP_EEDO	    0x00000001	/* EEPROM Data Out		    */


/*****************************************************************************/
/*                                                                           */
/*   SAR local SRAM layout for 128k work SRAM                                */
/*                                                                           */
/*****************************************************************************/

#define SAR_SRAM_SCD_SIZE        12
#define SAR_SRAM_TCT_SIZE         8
#define SAR_SRAM_RCT_SIZE         4

#define SAR_SRAM_TCT_128_BASE    0x00000
#define SAR_SRAM_TCT_128_TOP     0x01fff
#define SAR_SRAM_RCT_128_BASE    0x02000
#define SAR_SRAM_RCT_128_TOP     0x02fff
#define SAR_SRAM_FB0_128_BASE    0x03000
#define SAR_SRAM_FB0_128_TOP     0x033ff
#define SAR_SRAM_FB1_128_BASE    0x03400
#define SAR_SRAM_FB1_128_TOP     0x037ff
#define SAR_SRAM_FB2_128_BASE    0x03800
#define SAR_SRAM_FB2_128_TOP     0x03bff
#define SAR_SRAM_FB3_128_BASE    0x03c00
#define SAR_SRAM_FB3_128_TOP     0x03fff
#define SAR_SRAM_SCD_128_BASE    0x04000
#define SAR_SRAM_SCD_128_TOP     0x07fff
#define SAR_SRAM_TST1_128_BASE   0x08000
#define SAR_SRAM_TST1_128_TOP    0x0bfff
#define SAR_SRAM_TST2_128_BASE   0x0c000
#define SAR_SRAM_TST2_128_TOP    0x0ffff
#define SAR_SRAM_ABRSTD_128_BASE 0x10000
#define SAR_SRAM_ABRSTD_128_TOP  0x13fff
#define SAR_SRAM_RT_128_BASE     0x14000
#define SAR_SRAM_RT_128_TOP      0x15fff

#define SAR_SRAM_FIFO_128_BASE   0x18000
#define SAR_SRAM_FIFO_128_TOP    0x1ffff


/*****************************************************************************/
/*                                                                           */
/*   SAR local SRAM layout for 32k work SRAM                                 */
/*                                                                           */
/*****************************************************************************/

#define SAR_SRAM_TCT_32_BASE     0x00000
#define SAR_SRAM_TCT_32_TOP      0x00fff
#define SAR_SRAM_RCT_32_BASE     0x01000
#define SAR_SRAM_RCT_32_TOP      0x017ff
#define SAR_SRAM_FB0_32_BASE     0x01800
#define SAR_SRAM_FB0_32_TOP      0x01bff
#define SAR_SRAM_FB1_32_BASE     0x01c00
#define SAR_SRAM_FB1_32_TOP      0x01fff
#define SAR_SRAM_FB2_32_BASE     0x02000
#define SAR_SRAM_FB2_32_TOP      0x023ff
#define SAR_SRAM_FB3_32_BASE     0x02400
#define SAR_SRAM_FB3_32_TOP      0x027ff
#define SAR_SRAM_SCD_32_BASE     0x02800
#define SAR_SRAM_SCD_32_TOP      0x03fff
#define SAR_SRAM_TST1_32_BASE    0x04000
#define SAR_SRAM_TST1_32_TOP     0x04fff
#define SAR_SRAM_TST2_32_BASE    0x05000
#define SAR_SRAM_TST2_32_TOP     0x05fff
#define SAR_SRAM_ABRSTD_32_BASE  0x06000
#define SAR_SRAM_ABRSTD_32_TOP   0x067ff
#define SAR_SRAM_RT_32_BASE      0x06800
#define SAR_SRAM_RT_32_TOP       0x06fff
#define SAR_SRAM_FIFO_32_BASE    0x07000
#define SAR_SRAM_FIFO_32_TOP     0x07fff


/*****************************************************************************/
/*                                                                           */
/*   TSR - Transmit Status Request                                           */
/*                                                                           */
/*****************************************************************************/

#define SAR_TSR_TYPE_TSR  0x80000000
#define SAR_TSR_TYPE_TBD  0x00000000
#define SAR_TSR_TSIF      0x20000000
#define SAR_TSR_TAG_MASK  0x01F00000


/*****************************************************************************/
/*                                                                           */
/*   TBD - Transmit Buffer Descriptor                                        */
/*                                                                           */
/*****************************************************************************/

#define SAR_TBD_EPDU      0x40000000
#define SAR_TBD_TSIF      0x20000000
#define SAR_TBD_OAM       0x10000000
#define SAR_TBD_AAL0      0x00000000
#define SAR_TBD_AAL34     0x04000000
#define SAR_TBD_AAL5      0x08000000
#define SAR_TBD_GTSI      0x02000000
#define SAR_TBD_TAG_MASK  0x01F00000

#define SAR_TBD_VPI_MASK  0x0FF00000
#define SAR_TBD_VCI_MASK  0x000FFFF0
#define SAR_TBD_VC_MASK   (SAR_TBD_VPI_MASK | SAR_TBD_VCI_MASK)

#define SAR_TBD_VPI_SHIFT 20
#define SAR_TBD_VCI_SHIFT 4


/*****************************************************************************/
/*                                                                           */
/*   RXFD - Receive FIFO Descriptor                                          */
/*                                                                           */
/*****************************************************************************/

#define SAR_RXFD_SIZE_MASK     0x0F000000
#define SAR_RXFD_SIZE_512      0x00000000  /* 512 words                      */
#define SAR_RXFD_SIZE_1K       0x01000000  /* 1k words                       */
#define SAR_RXFD_SIZE_2K       0x02000000  /* 2k words                       */
#define SAR_RXFD_SIZE_4K       0x03000000  /* 4k words                       */
#define SAR_RXFD_SIZE_8K       0x04000000  /* 8k words                       */
#define SAR_RXFD_SIZE_16K      0x05000000  /* 16k words                      */
#define SAR_RXFD_SIZE_32K      0x06000000  /* 32k words                      */
#define SAR_RXFD_SIZE_64K      0x07000000  /* 64k words                      */
#define SAR_RXFD_SIZE_128K     0x08000000  /* 128k words                     */
#define SAR_RXFD_SIZE_256K     0x09000000  /* 256k words                     */
#define SAR_RXFD_ADDR_MASK     0x001ffc00


/*****************************************************************************/
/*                                                                           */
/*   ABRSTD - ABR + VBR Schedule Tables                                      */
/*                                                                           */
/*****************************************************************************/

#define SAR_ABRSTD_SIZE_MASK   0x07000000
#define SAR_ABRSTD_SIZE_512    0x00000000  /* 512 words                      */
#define SAR_ABRSTD_SIZE_1K     0x01000000  /* 1k words                       */
#define SAR_ABRSTD_SIZE_2K     0x02000000  /* 2k words                       */
#define SAR_ABRSTD_SIZE_4K     0x03000000  /* 4k words                       */
#define SAR_ABRSTD_SIZE_8K     0x04000000  /* 8k words                       */
#define SAR_ABRSTD_SIZE_16K    0x05000000  /* 16k words                      */
#define SAR_ABRSTD_ADDR_MASK   0x001ffc00


/*****************************************************************************/
/*                                                                           */
/*   RCTE - Receive Connection Table Entry                                   */
/*                                                                           */
/*****************************************************************************/

#define SAR_RCTE_IL_MASK       0xE0000000  /* inactivity limit               */
#define SAR_RCTE_IC_MASK       0x1C000000  /* inactivity count               */
#define SAR_RCTE_RSVD          0x02000000  /* reserved                       */
#define SAR_RCTE_LCD           0x01000000  /* last cell data                 */
#define SAR_RCTE_CI_VC         0x00800000  /* EFCI in previous cell of VC    */
#define SAR_RCTE_FBP_01        0x00000000  /* 1. cell->FBQ0, others->FBQ1    */
#define SAR_RCTE_FBP_1         0x00200000  /* use FBQ 1 for all cells        */
#define SAR_RCTE_FBP_2         0x00400000  /* use FBQ 2 for all cells        */
#define SAR_RCTE_FBP_3         0x00600000  /* use FBQ 3 for all cells        */
#define SAR_RCTE_NZ_GFC        0x00100000  /* non zero GFC in all cell of VC */
#define SAR_RCTE_CONNECTOPEN   0x00080000  /* VC is open                     */
#define SAR_RCTE_AAL_MASK      0x00070000  /* mask for AAL type field s.b.   */
#define SAR_RCTE_RAWCELLINTEN  0x00008000  /* raw cell interrupt enable      */
#define SAR_RCTE_RXCONCELLADDR 0x00004000  /* RX constant cell address       */
#define SAR_RCTE_BUFFSTAT_MASK 0x00003000  /* buffer status                  */
#define SAR_RCTE_EFCI          0x00000800  /* EFCI Congestion flag           */
#define SAR_RCTE_CLP           0x00000400  /* Cell Loss Priority flag        */
#define SAR_RCTE_CRC           0x00000200  /* Recieved CRC Error             */
#define SAR_RCTE_CELLCNT_MASK  0x000001FF  /* cell Count                     */

#define SAR_RCTE_AAL0          0x00000000  /* AAL types for ALL field        */
#define SAR_RCTE_AAL34         0x00010000
#define SAR_RCTE_AAL5          0x00020000
#define SAR_RCTE_RCQ           0x00030000
#define SAR_RCTE_OAM           0x00040000

#define TCMDQ_START		0x01000000
#define TCMDQ_LACR		0x02000000
#define TCMDQ_START_LACR	0x03000000
#define TCMDQ_INIT_ER		0x04000000
#define TCMDQ_HALT		0x05000000


struct idt77252_skb_prv {
	struct scqe	tbd;	/* Transmit Buffer Descriptor */
	dma_addr_t	paddr;	/* DMA handle */
	u32		pool;	/* sb_pool handle */
};

#define IDT77252_PRV_TBD(skb)	\
	(((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd)
#define IDT77252_PRV_PADDR(skb)	\
	(((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr)
#define IDT77252_PRV_POOL(skb)	\
	(((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool)

/*****************************************************************************/
/*                                                                           */
/*   PCI related items                                                       */
/*                                                                           */
/*****************************************************************************/

#ifndef PCI_VENDOR_ID_IDT
#define PCI_VENDOR_ID_IDT 0x111D
#endif /* PCI_VENDOR_ID_IDT */

#ifndef PCI_DEVICE_ID_IDT_IDT77252
#define PCI_DEVICE_ID_IDT_IDT77252 0x0003
#endif /* PCI_DEVICE_ID_IDT_IDT772052 */


#endif /* !(_IDT77252_H) */