idt77252.h

linux和2410结合开发 用他可以生成2410所需的zImage文件

	struct rsq_entry	*next;
	struct rsq_entry	*last;
	dma_addr_t		paddr;
} rsq_info;


/*****************************************************************************/
/*                                                                           */
/*   TSQ - Transmit Status Queue                                             */
/*                                                                           */
/*****************************************************************************/

#define SAR_TSQE_INVALID         0x80000000
#define SAR_TSQE_TIMESTAMP       0x00FFFFFF
#define SAR_TSQE_TYPE		 0x60000000
#define SAR_TSQE_TYPE_TIMER      0x00000000
#define SAR_TSQE_TYPE_TSR        0x20000000
#define SAR_TSQE_TYPE_IDLE       0x40000000
#define SAR_TSQE_TYPE_TBD_COMP   0x60000000

#define SAR_TSQE_TAG(stat)	(((stat) >> 24) & 0x1f)

#define TSQSIZE            8192
#define TSQ_NUM_ENTRIES    1024
#define TSQ_ALIGNMENT      8192

struct tsq_entry
{
	u32			word_1;
	u32			word_2;
};

struct tsq_info
{
	struct tsq_entry	*base;
	struct tsq_entry	*next;
	struct tsq_entry	*last;
	dma_addr_t		paddr;
};

struct tst_info
{
	struct vc_map		*vc;
	u32			tste;
};

#define TSTE_MASK		0x601fffff

#define TSTE_OPC_MASK		0x60000000
#define TSTE_OPC_NULL		0x00000000
#define TSTE_OPC_CBR		0x20000000
#define TSTE_OPC_VAR		0x40000000
#define TSTE_OPC_JMP		0x60000000

#define TSTE_PUSH_IDLE		0x01000000
#define TSTE_PUSH_ACTIVE	0x02000000

#define TST_SWITCH_DONE		0
#define TST_SWITCH_PENDING	1
#define TST_SWITCH_WAIT		2

#define FBQ_SHIFT		9
#define FBQ_SIZE		(1 << FBQ_SHIFT)
#define FBQ_MASK		(FBQ_SIZE - 1)

struct sb_pool
{
	unsigned int		index;
	struct sk_buff		*skb[FBQ_SIZE];
};

#define POOL_HANDLE(queue, index)	(((queue + 1) << 16) | (index))
#define POOL_QUEUE(handle)		(((handle) >> 16) - 1)
#define POOL_INDEX(handle)		((handle) & 0xffff)

struct idt77252_dev
{
        struct tsq_info		tsq;		/* Transmit Status Queue */
        struct rsq_info		rsq;		/* Receive Status Queue */

	struct pci_dev		*pcidev;	/* PCI handle (desriptor) */
	struct atm_dev		*atmdev;	/* ATM device desriptor */

	unsigned long		membase;	/* SAR's memory base address */
	unsigned long		srambase;	/* SAR's sram  base address */
	unsigned long		fbq[4];		/* FBQ fill addresses */

	struct semaphore	mutex;
	spinlock_t		cmd_lock;	/* for r/w utility/sram */

	unsigned long		softstat;
	unsigned long		flags;		/* see blow */

	struct tq_struct	tqueue;

	unsigned long		tct_base;	/* TCT base address in SRAM */
        unsigned long		rct_base;	/* RCT base address in SRAM */
        unsigned long		rt_base;	/* Rate Table base in SRAM */
        unsigned long		scd_base;	/* SCD base address in SRAM */
        unsigned long		tst[2];		/* TST base address in SRAM */
	unsigned long		abrst_base;	/* ABRST base address in SRAM */
        unsigned long		fifo_base;	/* RX FIFO base in SRAM */

	unsigned long		irqstat[16];

	unsigned int		sramsize;	/* SAR's sram size */

        unsigned int		tct_size;	/* total TCT entries */
        unsigned int		rct_size;	/* total RCT entries */
        unsigned int		scd_size;	/* length of SCD */
        unsigned int		tst_size;	/* total TST entries */
        unsigned int		tst_free;	/* free TSTEs in TST */
        unsigned int		abrst_size;	/* size of ABRST in words */
        unsigned int		fifo_size;	/* size of RX FIFO in words */

        unsigned int		vpibits;	/* Bits used for VPI index */
        unsigned int		vcibits;	/* Bits used for VCI index */
        unsigned int		vcimask;	/* Mask for VCI index */

	unsigned int		utopia_pcr;	/* Utopia Itf's Cell Rate */
	unsigned int		link_pcr;	/* PHY's Peek Cell Rate */

	struct vc_map		**vcs;		/* Open Connections */
	struct vc_map		**scd2vc;	/* SCD to Connection map */

	struct tst_info		*soft_tst;	/* TST to Connection map */
	unsigned int		tst_index;	/* Current TST in use */
	struct timer_list	tst_timer;
	spinlock_t		tst_lock;
	unsigned long		tst_state;

	struct sb_pool		sbpool[4];	/* Pool of RX skbuffs */
	struct sk_buff		*raw_cell_head; /* Pointer to raw cell queue */
	u32			*raw_cell_hnd;	/* Pointer to RCQ handle */
	dma_addr_t		raw_cell_paddr;

	int			index;		/* SAR's ID */
	int			revision;	/* chip revision */

	char			name[16];	/* Device name */

	struct idt77252_dev	*next;
};


/* definition for flag field above */
#define IDT77252_BIT_INIT		1
#define IDT77252_BIT_INTERRUPT		2


#define ATM_CELL_PAYLOAD         48

#define FREEBUF_ALIGNMENT        16

/*****************************************************************************/
/*                                                                           */
/* Makros                                                                    */
/*                                                                           */
/*****************************************************************************/
#define ALIGN_ADDRESS(addr, alignment) \
        ((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1))


/*****************************************************************************/
/*                                                                           */
/*   ABR SAR Network operation Register                                      */
/*                                                                           */
/*****************************************************************************/

#define SAR_REG_DR0	(card->membase + 0x00)
#define SAR_REG_DR1	(card->membase + 0x04)
#define SAR_REG_DR2	(card->membase + 0x08)
#define SAR_REG_DR3	(card->membase + 0x0C)
#define SAR_REG_CMD	(card->membase + 0x10)
#define SAR_REG_CFG	(card->membase + 0x14)
#define SAR_REG_STAT	(card->membase + 0x18)
#define SAR_REG_RSQB	(card->membase + 0x1C)
#define SAR_REG_RSQT	(card->membase + 0x20)
#define SAR_REG_RSQH	(card->membase + 0x24)
#define SAR_REG_CDC	(card->membase + 0x28)
#define SAR_REG_VPEC	(card->membase + 0x2C)
#define SAR_REG_ICC	(card->membase + 0x30)
#define SAR_REG_RAWCT	(card->membase + 0x34)
#define SAR_REG_TMR	(card->membase + 0x38)
#define SAR_REG_TSTB	(card->membase + 0x3C)
#define SAR_REG_TSQB	(card->membase + 0x40)
#define SAR_REG_TSQT	(card->membase + 0x44)
#define SAR_REG_TSQH	(card->membase + 0x48)
#define SAR_REG_GP	(card->membase + 0x4C)
#define SAR_REG_VPM	(card->membase + 0x50)
#define SAR_REG_RXFD	(card->membase + 0x54)
#define SAR_REG_RXFT	(card->membase + 0x58)
#define SAR_REG_RXFH	(card->membase + 0x5C)
#define SAR_REG_RAWHND	(card->membase + 0x60)
#define SAR_REG_RXSTAT	(card->membase + 0x64)
#define SAR_REG_ABRSTD	(card->membase + 0x68)
#define SAR_REG_ABRRQ	(card->membase + 0x6C)
#define SAR_REG_VBRRQ	(card->membase + 0x70)
#define SAR_REG_RTBL	(card->membase + 0x74)
#define SAR_REG_MDFCT	(card->membase + 0x78)
#define SAR_REG_TXSTAT	(card->membase + 0x7C)
#define SAR_REG_TCMDQ	(card->membase + 0x80)
#define SAR_REG_IRCP	(card->membase + 0x84)
#define SAR_REG_FBQP0	(card->membase + 0x88)
#define SAR_REG_FBQP1	(card->membase + 0x8C)
#define SAR_REG_FBQP2	(card->membase + 0x90)
#define SAR_REG_FBQP3	(card->membase + 0x94)
#define SAR_REG_FBQS0	(card->membase + 0x98)
#define SAR_REG_FBQS1	(card->membase + 0x9C)
#define SAR_REG_FBQS2	(card->membase + 0xA0)
#define SAR_REG_FBQS3	(card->membase + 0xA4)
#define SAR_REG_FBQWP0	(card->membase + 0xA8)
#define SAR_REG_FBQWP1	(card->membase + 0xAC)
#define SAR_REG_FBQWP2	(card->membase + 0xB0)
#define SAR_REG_FBQWP3	(card->membase + 0xB4)
#define SAR_REG_NOW	(card->membase + 0xB8)


/*****************************************************************************/
/*                                                                           */
/*   Commands                                                                */
/*                                                                           */
/*****************************************************************************/

#define SAR_CMD_NO_OPERATION         0x00000000
#define SAR_CMD_OPENCLOSE_CONNECTION 0x20000000
#define SAR_CMD_WRITE_SRAM           0x40000000
#define SAR_CMD_READ_SRAM            0x50000000
#define SAR_CMD_READ_UTILITY         0x80000000
#define SAR_CMD_WRITE_UTILITY        0x90000000

#define SAR_CMD_OPEN_CONNECTION     (SAR_CMD_OPENCLOSE_CONNECTION | 0x00080000)
#define SAR_CMD_CLOSE_CONNECTION     SAR_CMD_OPENCLOSE_CONNECTION


/*****************************************************************************/
/*                                                                           */
/*   Configuration Register bits                                             */
/*                                                                           */
/*****************************************************************************/

#define SAR_CFG_SWRST          0x80000000  /* Software reset                 */
#define SAR_CFG_LOOP           0x40000000  /* Internal Loopback              */
#define SAR_CFG_RXPTH          0x20000000  /* Receive Path Enable            */
#define SAR_CFG_IDLE_CLP       0x10000000  /* SAR set CLP Bits of Null Cells */
#define SAR_CFG_TX_FIFO_SIZE_1 0x04000000  /* TX FIFO Size = 1 cell          */
#define SAR_CFG_TX_FIFO_SIZE_2 0x08000000  /* TX FIFO Size = 2 cells         */
#define SAR_CFG_TX_FIFO_SIZE_4 0x0C000000  /* TX FIFO Size = 4 cells         */
#define SAR_CFG_TX_FIFO_SIZE_9 0x00000000  /* TX FIFO Size = 9 cells (full)  */
#define SAR_CFG_NO_IDLE        0x02000000  /* SAR sends no Null Cells        */
#define SAR_CFG_RSVD1          0x01000000  /* Reserved                       */
#define SAR_CFG_RXSTQ_SIZE_2k  0x00000000  /* RX Stat Queue Size = 2048 byte */
#define SAR_CFG_RXSTQ_SIZE_4k  0x00400000  /* RX Stat Queue Size = 4096 byte */
#define SAR_CFG_RXSTQ_SIZE_8k  0x00800000  /* RX Stat Queue Size = 8192 byte */
#define SAR_CFG_RXSTQ_SIZE_R   0x00C00000  /* RX Stat Queue Size = reserved  */
#define SAR_CFG_ICAPT          0x00200000  /* accept Invalid Cells           */
#define SAR_CFG_IGGFC          0x00100000  /* Ignore GFC                     */
#define SAR_CFG_VPVCS_0        0x00000000  /* VPI/VCI Select bit range       */
#define SAR_CFG_VPVCS_1        0x00040000  /* VPI/VCI Select bit range       */
#define SAR_CFG_VPVCS_2        0x00080000  /* VPI/VCI Select bit range       */
#define SAR_CFG_VPVCS_8        0x000C0000  /* VPI/VCI Select bit range       */
#define SAR_CFG_CNTBL_1k       0x00000000  /* Connection Table Size          */
#define SAR_CFG_CNTBL_4k       0x00010000  /* Connection Table Size          */
#define SAR_CFG_CNTBL_16k      0x00020000  /* Connection Table Size          */
#define SAR_CFG_CNTBL_512      0x00030000  /* Connection Table Size          */
#define SAR_CFG_VPECA          0x00008000  /* VPI/VCI Error Cell Accept      */
#define SAR_CFG_RXINT_NOINT    0x00000000  /* No Interrupt on PDU received   */
#define SAR_CFG_RXINT_NODELAY  0x00001000  /* Interrupt without delay to host*/
#define SAR_CFG_RXINT_256US    0x00002000  /* Interrupt with delay 256 usec  */
#define SAR_CFG_RXINT_505US    0x00003000  /* Interrupt with delay 505 usec  */
#define SAR_CFG_RXINT_742US    0x00004000  /* Interrupt with delay 742 usec  */
#define SAR_CFG_RAWIE          0x00000800  /* Raw Cell Queue Interrupt Enable*/
#define SAR_CFG_RQFIE          0x00000400  /* RSQ Almost Full Int Enable     */