qla1280.h

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       #define WRT_REG_DWORD(addr, data) writel((data), (unsigned long) (addr))
#else   /* MEMORY_MAPPED_IO */
#define RD_REG_BYTE(addr)         (inb((unsigned long)addr))
#define RD_REG_WORD(addr)         (inw((unsigned long)addr))
#define RD_REG_DWORD(addr)        (inl((unsigned long)addr))
#ifdef LINUX_IOPORTS
/* Parameters are reversed in Linux */
#define WRT_REG_BYTE(addr, data)  (outb(data,(unsigned long)addr))
#define WRT_REG_WORD(addr, data)  (outw(data,(unsigned long)addr))
#define WRT_REG_DWORD(addr, data) (outl(data,(unsigned long)addr))
#else
#define WRT_REG_BYTE(addr, data)  (outb((unsigned long)addr, data))
#define WRT_REG_WORD(addr, data)  (outw((unsigned long)addr, data))
#define WRT_REG_DWORD(addr, data) (outl((unsigned long)addr, data))
#endif
#endif  /* MEMORY_MAPPED_IO */
#endif    /* QL_DEBUG_LEVEL_1 */

/*
 * Host adapter default definitions.
 */
#define MAX_BUSES       2             /* 2 */
#define MAX_B_BITS      1

#define MAX_TARGETS     16             /* 16 */
#define MAX_T_BITS      4              /* 4 */

#define MAX_LUNS        8              /* 32 */
#define MAX_L_BITS      3               /* 5 */

/*
 * Watchdog time quantum
 */
#define QLA1280_WDG_TIME_QUANTUM   5    /* In seconds */

/* Command retry count (0-65535) */
#define COMMAND_RETRY_COUNT   255

/* Maximum outstanding commands in ISP queues (1-65535) */
#define MAX_OUTSTANDING_COMMANDS   512

/* ISP request and response entry counts (37-65535) */
#define REQUEST_ENTRY_CNT       256     /* Number of request entries. */
#define RESPONSE_ENTRY_CNT      16      /* Number of response entries. */

/* Maximum equipage per controller */
#define MAX_EQ          (MAX_BUSES * MAX_TARGETS * MAX_LUNS)

/* Number of segments 1 - 65535 */
#define SG_SEGMENTS     32             /* Cmd entry + 6 continuations */


/*
 * SCSI Request Block structure
 */
typedef struct srb
{
    Scsi_Cmnd  *cmd;                 /* (4) SCSI command block */
    struct srb  *s_next;             /* (4) Next block on LU queue */
    struct srb  *s_prev;             /* (4) Previous block on LU queue */
    uint8_t     flags;               /* (1) Status flags. */
    uint8_t     dir;                 /* direction of transfer */
    uint8_t     unused[2];
    u_long      r_start;             /* jiffies at start of request */
    u_long      u_start;             /* jiffies when sent to F/W    */
}srb_t;

/*
 * SRB flag definitions
 */
#define SRB_TIMEOUT     BIT_0           /* Command timed out */
#define SRB_SENT        BIT_1           /* Command sent to ISP */
#define SRB_ABORT_PENDING     BIT_2     /* Command abort sent to device */
#define SRB_ABORTED     BIT_3           /* Command aborted command already */


/*
 * Logical Unit Queue structure
 */
typedef struct scsi_lu
{
    srb_t           *q_first;           /* First block on LU queue */
    srb_t           *q_last;            /* Last block on LU queue */
    uint8_t         q_flag;             /* LU queue state flags */
    uint8_t         q_sense[16];        /* sense data */
    u_long          io_cnt;             /* total xfer count */
    u_long          resp_time;          /* total response time (start - finish) */
    u_long          act_time;           /* total actived time (minus queuing time) */
    u_long          w_cnt;              /* total writes */
    u_long          r_cnt;              /* total reads */
    uint16_t        q_outcnt;           /* Pending jobs for this LU */
#if QL1280_TARGET_MODE_SUPPORT
    void            (*q_func)();        /* Target driver event handler */
    int32_t         q_param;            /* Target driver event param */
    uint8_t         q_lock;            /* Device Queue Lock */
#endif
}scsi_lu_t;

/*
 * Logical Unit flags 
 */
#define QLA1280_QBUSY   BIT_0
#define QLA1280_QWAIT   BIT_1
#define QLA1280_QSUSP   BIT_2
#define QLA1280_QSENSE  BIT_3           /* Sense data cache valid */
#define QLA1280_QRESET  BIT_4
#define QLA1280_QHBA    BIT_5
#define QLA1280_BSUSP   BIT_6           /* controller is suspended */
#define QLA1280_BREM    BIT_7           /* controller is removed */

/*
 *  ISP PCI Configuration Register Set
 */
typedef volatile struct
{
    uint16_t vendor_id;                 /* 0x0 */
    uint16_t device_id;                 /* 0x2 */
    uint16_t command;                   /* 0x4 */
    uint16_t status;                    /* 0x6 */
    uint8_t revision_id;                /* 0x8 */
    uint8_t programming_interface;      /* 0x9 */
    uint8_t sub_class;                  /* 0xa */
    uint8_t base_class;                 /* 0xb */
    uint8_t cache_line;                 /* 0xc */
    uint8_t latency_timer;              /* 0xd */
    uint8_t header_type;                /* 0xe */
    uint8_t bist;                       /* 0xf */
    uint32_t base_port;                  /* 0x10 */
    uint32_t mem_base_addr;              /* 0x14 */
    uint32_t base_addr[4];               /* 0x18-0x24 */
    uint32_t reserved_1[2];              /* 0x28-0x2c */
    uint16_t expansion_rom;             /* 0x30 */
    uint32_t reserved_2[2];              /* 0x34-0x38 */
    uint8_t interrupt_line;             /* 0x3c */
    uint8_t interrupt_pin;              /* 0x3d */
    uint8_t min_grant;                  /* 0x3e */
    uint8_t max_latency;                /* 0x3f */
}config_reg_t;

/*
 *  ISP I/O Register Set structure definitions.
 */
typedef volatile struct
{
    uint16_t id_l;                      /* ID low */
    uint16_t id_h;                      /* ID high */
    uint16_t cfg_0;                     /* Configuration 0 */
    uint16_t cfg_1;                     /* Configuration 1 */
    uint16_t ictrl;                     /* Interface control */
        #define ISP_RESET       BIT_0   /* ISP soft reset */
        #define ISP_EN_INT      BIT_1   /* ISP enable interrupts. */
        #define ISP_EN_RISC     BIT_2   /* ISP enable RISC interrupts. */
    uint16_t istatus;                   /* Interface status */
        #define PCI_64BIT_SLOT  BIT_14  /* PCI 64-bit slot indicator. */
        #define RISC_INT        BIT_2   /* RISC interrupt */
        #define PCI_INT         BIT_1   /* PCI interrupt */
    uint16_t semaphore;                 /* Semaphore */
    uint16_t nvram;                     /* NVRAM register. */
        #define NV_DESELECT     0
        #define NV_CLOCK        BIT_0
        #define NV_SELECT       BIT_1
        #define NV_DATA_OUT     BIT_2
        #define NV_DATA_IN      BIT_3
    uint16_t flash_data;                /* Flash BIOS data */
    uint16_t flash_address;             /* Flash BIOS address */

    uint16_t unused_1[0x2e];            /* 0x14-0x6f Gap */

    uint16_t mailbox0;                  /* Mailbox 0 */
    uint16_t mailbox1;                  /* Mailbox 1 */
    uint16_t mailbox2;                  /* Mailbox 2 */
    uint16_t mailbox3;                  /* Mailbox 3 */
    uint16_t mailbox4;                  /* Mailbox 4 */
    uint16_t mailbox5;                  /* Mailbox 5 */
    uint16_t mailbox6;                  /* Mailbox 6 */
    uint16_t mailbox7;                  /* Mailbox 7 */

    uint16_t unused_2[0x20];            /* 0x80-0xbf Gap */

    uint16_t host_cmd;                  /* Host command and control */
        #define HOST_INT      BIT_7     /* host interrupt bit */
        #define BIOS_ENABLE   BIT_0

    uint16_t unused_6[0x5];             /* 0xc2-0xcb Gap */

    uint16_t gpio_data;
    uint16_t gpio_enable;

    uint16_t unused_7[0x11];			/* d0-f0	*/
    uint16_t scsiControlPins;           /* f2 */

}device_reg_t;

#define MAILBOX_REGISTER_COUNT  8

/*
 *  ISP product identification definitions in mailboxes after reset.
 */
#define PROD_ID_1           0x4953
#define PROD_ID_2           0x0000
#define PROD_ID_2a          0x5020
#define PROD_ID_3           0x2020
#define PROD_ID_4           0x1

/*
 * ISP host command and control register command definitions
 */
#define HC_RESET_RISC       0x1000      /* Reset RISC */
#define HC_PAUSE_RISC       0x2000      /* Pause RISC */
#define HC_RELEASE_RISC     0x3000      /* Release RISC from reset. */
#define HC_SET_HOST_INT     0x5000      /* Set host interrupt */
#define HC_CLR_HOST_INT     0x6000      /* Clear HOST interrupt */
#define HC_CLR_RISC_INT     0x7000      /* Clear RISC interrupt */
#define HC_DISABLE_BIOS     0x9000      /* Disable BIOS. */

/*
 * ISP mailbox Self-Test status codes
 */
#define MBS_FRM_ALIVE       0           /* Firmware Alive. */
#define MBS_CHKSUM_ERR      1           /* Checksum Error. */
#define MBS_SHADOW_LD_ERR   2           /* Shadow Load Error. */
#define MBS_BUSY            4           /* Busy. */

/*
 * ISP mailbox command complete status codes
 */
#define MBS_CMD_CMP         0x4000      /* Command Complete. */
#define MBS_INV_CMD         0x4001      /* Invalid Command. */
#define MBS_HOST_INF_ERR    0x4002      /* Host Interface Error. */
#define MBS_TEST_FAILED     0x4003      /* Test Failed. */
#define MBS_CMD_ERR         0x4005      /* Command Error. */
#define MBS_CMD_PARAM_ERR   0x4006      /* Command Parameter Error. */

/*
 * ISP mailbox asynchronous event status codes
 */
#define MBA_ASYNC_EVENT         0x8000  /* Asynchronous event. */
#define MBA_BUS_RESET           0x8001  /* SCSI Bus Reset. */
#define MBA_SYSTEM_ERR          0x8002  /* System Error. */
#define MBA_REQ_TRANSFER_ERR    0x8003  /* Request Transfer Error. */
#define MBA_RSP_TRANSFER_ERR    0x8004  /* Response Transfer Error. */
#define MBA_WAKEUP_THRES        0x8005  /* Request Queue Wake-up. */
#define MBA_TIMEOUT_RESET       0x8006  /* Execution Timeout Reset. */
#define MBA_DEVICE_RESET        0x8007  /* Bus Device Reset. */
#define MBA_BUS_MODE_CHANGE     0x800E  /* SCSI bus mode transition. */
#define MBA_SCSI_COMPLETION     0x8020  /* Completion response. */

/*
 * ISP mailbox commands
 */
#define MBC_NOP                     0       /* No Operation. */
#define MBC_LOAD_RAM                1       /* Load RAM. */
#define MBC_EXECUTE_FIRMWARE        2       /* Execute firmware. */
#define MBC_WRITE_RAM_WORD          4       /* Write ram word. */
#define MBC_READ_RAM_WORD           5       /* Read ram word. */
#define MBC_MAILBOX_REGISTER_TEST   6       /* Wrap incoming mailboxes */
#define MBC_VERIFY_CHECKSUM         7       /* Verify checksum. */
#define MBC_ABOUT_FIRMWARE          8       /* Get firmware revision. */
#define MBC_INIT_REQUEST_QUEUE      0x10    /* Initialize request queue. */
#define MBC_INIT_RESPONSE_QUEUE     0x11    /* Initialize response queue. */
#define MBC_EXECUTE_IOCB            0x12    /* Execute IOCB command. */
#define MBC_ABORT_COMMAND           0x15    /* Abort IOCB command. */
#define MBC_ABORT_DEVICE            0x16    /* Abort device (ID/LUN). */
#define MBC_ABORT_TARGET            0x17    /* Abort target (ID). */
#define MBC_BUS_RESET               0x18    /* SCSI bus reset. */
#define MBC_GET_RETRY_COUNT         0x22    /* Get retry count and delay. */
#define MBC_GET_TARGET_PARAMETERS   0x28    /* Get target parameters. */
#define MBC_SET_INITIATOR_ID        0x30    /* Set initiator SCSI ID. */
#define MBC_SET_SELECTION_TIMEOUT   0x31    /* Set selection timeout. */
#define MBC_SET_RETRY_COUNT         0x32    /* Set retry count and delay. */
#define MBC_SET_TAG_AGE_LIMIT       0x33    /* Set tag age limit. */
#define MBC_SET_CLOCK_RATE          0x34    /* Set clock rate. */
#define MBC_SET_ACTIVE_NEGATION     0x35    /* Set active negation state. */
#define MBC_SET_ASYNC_DATA_SETUP    0x36    /* Set async data setup time. */
#define MBC_SET_PCI_CONTROL         0x37    /* Set BUS control parameters. */
#define MBC_SET_TARGET_PARAMETERS   0x38    /* Set target parameters. */
#define MBC_SET_DEVICE_QUEUE        0x39    /* Set device queue parameters */
#define MBC_SET_SYSTEM_PARAMETER    0x45    /* Set system parameter word. */
#define MBC_SET_FIRMWARE_FEATURES   0x4A    /* Set firmware feature word. */
#define MBC_INIT_REQUEST_QUEUE_A64  0x52    /* Initialize request queue A64 */
#define MBC_INIT_RESPONSE_QUEUE_A64 0x53    /* Initialize response q A64. */
#define MBC_ENABLE_TARGET_MODE      0x55    /* Enable target mode. */

/*
 * ISP Get/Set Target Parameters mailbox command control flags.
 */
#define TP_RENEGOTIATE          BIT_8   /* Renegotiate on error. */
#define TP_STOP_QUEUE           BIT_9   /* Stop que on check condition */
#define TP_AUTO_REQUEST_SENSE   BIT_10  /* Automatic request sense. */
#define TP_TAGGED_QUEUE         BIT_11  /* Tagged queuing. */
#define TP_SYNC                 BIT_12  /* Synchronous data transfers. */
#define TP_WIDE                 BIT_13  /* Wide data transfers. */
#define TP_PARITY               BIT_14  /* Parity checking. */
#define TP_DISCONNECT           BIT_15  /* Disconnect privilege. */

/*
 * NVRAM Command values.
 */
#define NV_START_BIT            BIT_2
#define NV_WRITE_OP             (BIT_26+BIT_24)
#define NV_READ_OP              (BIT_26+BIT_25)
#define NV_ERASE_OP             (BIT_26+BIT_25+BIT_24)
#define NV_MASK_OP              (BIT_26+BIT_25+BIT_24)
#define NV_DELAY_COUNT          10

/*
 *  QLogic ISP1280 NVRAM structure definition.
 */
typedef struct
{
    uint8_t id[4];                                  /* 0, 1, 2, 3 */
    uint8_t version;                                /* 4 */

    struct
    {
        uint8_t bios_configuration_mode     :2;
        uint8_t bios_disable                :1;
        uint8_t selectable_scsi_boot_enable :1;
        uint8_t cd_rom_boot_enable          :1;
        uint8_t disable_loading_risc_code   :1;
        uint8_t enable_64bit_addressing     :1;