aacraid.h

linux和2410结合开发 用他可以生成2410所需的zImage文件

 *	Define which interrupt handler needs to be installed
 */

struct aac_driver_ident
{
	u16	vendor;
	u16	device;
	u16	subsystem_vendor;
	u16	subsystem_device;
	int 	(*init)(struct aac_dev *dev, unsigned long num);
	char *	name;
	char *	vname;
	char *	model;
};

/*
 *	The adapter interface specs all queues to be located in the same
 *	physically contigous block. The host structure that defines the
 *	commuication queues will assume they are each a seperate physically
 *	contigous memory region that will support them all being one big
 *	contigous block. 
 *	There is a command and response queue for each level and direction of
 *	commuication. These regions are accessed by both the host and adapter.
 */
 
struct aac_queue {
	u64		 	logical;		/* This is the address we give the adapter */
	struct aac_entry	*base;		   	/* This is the system virtual address */
	struct aac_qhdr 	headers;       		/* A pointer to the producer and consumer queue headers for this queue */
	u32	 		entries;	   	/* Number of queue entries on this queue */
	wait_queue_head_t	qfull;		      	/* Event to wait on if the queue is full */
	wait_queue_head_t	cmdready;	  	/* Indicates there is a Command ready from the adapter on this queue. */
                                        		/* This is only valid for adapter to host command queues. */                      
	spinlock_t	 	*lock;		     	/* Spinlock for this queue must take this lock before accessing the lock */
	spinlock_t		lockdata;		/* Actual lock (used only on one side of the lock) */
	unsigned long		SavedIrql;      	/* Previous IRQL when the spin lock is taken */
	u32			padding;		/* Padding - FIXME - can remove I believe */
	struct list_head 	cmdq;		   	/* A queue of FIBs which need to be prcessed by the FS thread. This is */
                                		        /* only valid for command queues which receive entries from the adapter. */
	struct list_head	pendingq;		/* A queue of outstanding fib's to the adapter. */
	unsigned long		numpending;		/* Number of entries on outstanding queue. */
	struct aac_dev *	dev;			/* Back pointer to adapter structure */
};

/*
 *	Message queues. The order here is important, see also the 
 *	queue type ordering
 */

struct aac_queue_block
{
	struct aac_queue queue[8];
};

/*
 *	SaP1 Message Unit Registers
 */
 
struct sa_drawbridge_CSR {
						//	 Offset |	Name
	u32	reserved[10];			//	00h-27h |   Reserved
	u8	LUT_Offset;			//		28h	|	Looup Table Offset
	u8	reserved1[3];			// 	29h-2bh	|	Reserved
	u32	LUT_Data;			//		2ch	|	Looup Table Data	
	u32	reserved2[26];			//	30h-97h	|	Reserved
	u16	PRICLEARIRQ;			//		98h	|	Primary Clear Irq
	u16	SECCLEARIRQ;			//		9ah	|	Secondary Clear Irq
	u16	PRISETIRQ;			//		9ch	|	Primary Set Irq
	u16	SECSETIRQ;			//		9eh	|	Secondary Set Irq
	u16	PRICLEARIRQMASK;		//		a0h	|	Primary Clear Irq Mask
	u16	SECCLEARIRQMASK;		//		a2h	|	Secondary Clear Irq Mask
	u16	PRISETIRQMASK;			//		a4h	|	Primary Set Irq Mask
	u16	SECSETIRQMASK;			//		a6h	|	Secondary Set Irq Mask
	u32	MAILBOX0;			//		a8h	|	Scratchpad 0
	u32	MAILBOX1;			//		ach	|	Scratchpad 1
	u32	MAILBOX2;			//		b0h	|	Scratchpad 2
	u32	MAILBOX3;			//		b4h	|	Scratchpad 3
	u32	MAILBOX4;			//		b8h	|	Scratchpad 4
	u32	MAILBOX5;			//		bch	|	Scratchpad 5
	u32	MAILBOX6;			//		c0h	|	Scratchpad 6
	u32	MAILBOX7;			//		c4h	|	Scratchpad 7

	u32	ROM_Setup_Data;			//		c8h | 	Rom Setup and Data
	u32	ROM_Control_Addr;		//		cch | 	Rom Control and Address

	u32	reserved3[12];			//	d0h-ffh	| 	reserved
	u32	LUT[64];			// 100h-1ffh|	Lookup Table Entries

	//
	//  TO DO
	//	need to add DMA, I2O, UART, etc registers form 80h to 364h
	//

};

#define Mailbox0	SaDbCSR.MAILBOX0
#define Mailbox1	SaDbCSR.MAILBOX1
#define Mailbox2	SaDbCSR.MAILBOX2
#define Mailbox3	SaDbCSR.MAILBOX3
#define Mailbox4	SaDbCSR.MAILBOX4
#define Mailbox5	SaDbCSR.MAILBOX5
#define Mailbox7	SaDbCSR.MAILBOX7
	
#define DoorbellReg_p SaDbCSR.PRISETIRQ
#define DoorbellReg_s SaDbCSR.SECSETIRQ
#define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ


#define	DOORBELL_0	cpu_to_le16(0x0001)
#define DOORBELL_1	cpu_to_le16(0x0002)
#define DOORBELL_2	cpu_to_le16(0x0004)
#define DOORBELL_3	cpu_to_le16(0x0008)
#define DOORBELL_4	cpu_to_le16(0x0010)
#define DOORBELL_5	cpu_to_le16(0x0020)
#define DOORBELL_6	cpu_to_le16(0x0040)

	
#define PrintfReady	DOORBELL_5
#define PrintfDone	DOORBELL_5
	
struct sa_registers {
	struct sa_drawbridge_CSR	SaDbCSR;			/* 98h - c4h */
};
	

#define Sa_MINIPORT_REVISION			1

#define sa_readw(AEP, CSR)		readl(&((AEP)->regs.sa->CSR))
#define sa_readl(AEP,  CSR)		readl(&((AEP)->regs.sa->CSR))
#define sa_writew(AEP, CSR, value)	writew(value, &((AEP)->regs.sa->CSR))
#define sa_writel(AEP, CSR, value)	writel(value, &((AEP)->regs.sa->CSR))

/*
 *	Rx Message Unit Registers
 */

struct rx_mu_registers {
						//	 Local	|   PCI*	|	Name
						//			|		|
	u32	ARSR;				//	1300h	|	00h	|	APIC Register Select Register
	u32	reserved0;			//	1304h	|	04h	|	Reserved
	u32	AWR;				//	1308h	|	08h	|	APIC Window Register
	u32	reserved1;			//	130Ch	|	0Ch	|	Reserved
	u32	IMRx[2];			//	1310h	|	10h	|	Inbound Message Registers
	u32	OMRx[2];			//	1318h	|	18h	|	Outbound Message Registers
	u32	IDR;				//	1320h	|	20h	|	Inbound Doorbell Register
	u32	IISR;				//	1324h	|	24h	|	Inbound Interrupt Status Register
	u32	IIMR;				//	1328h	|	28h	|	Inbound Interrupt Mask Register
	u32	ODR;				//	132Ch	|	2Ch	|	Outbound Doorbell Register
	u32	OISR;				//	1330h	|	30h	|	Outbound Interrupt Status Register
	u32	OIMR;				//	1334h	|	34h	|	Outbound Interrupt Mask Register
						// * Must access through ATU Inbound Translation Window
};

struct rx_inbound {
	u32	Mailbox[8];
};

#define	InboundMailbox0		IndexRegs.Mailbox[0]
#define	InboundMailbox1		IndexRegs.Mailbox[1]
#define	InboundMailbox2		IndexRegs.Mailbox[2]
#define	InboundMailbox3		IndexRegs.Mailbox[3]
#define	InboundMailbox4		IndexRegs.Mailbox[4]

#define	INBOUNDDOORBELL_0	cpu_to_le32(0x00000001)
#define INBOUNDDOORBELL_1	cpu_to_le32(0x00000002)
#define INBOUNDDOORBELL_2	cpu_to_le32(0x00000004)
#define INBOUNDDOORBELL_3	cpu_to_le32(0x00000008)
#define INBOUNDDOORBELL_4	cpu_to_le32(0x00000010)
#define INBOUNDDOORBELL_5	cpu_to_le32(0x00000020)
#define INBOUNDDOORBELL_6	cpu_to_le32(0x00000040)

#define	OUTBOUNDDOORBELL_0	cpu_to_le32(0x00000001)
#define OUTBOUNDDOORBELL_1	cpu_to_le32(0x00000002)
#define OUTBOUNDDOORBELL_2	cpu_to_le32(0x00000004)
#define OUTBOUNDDOORBELL_3	cpu_to_le32(0x00000008)
#define OUTBOUNDDOORBELL_4	cpu_to_le32(0x00000010)

#define InboundDoorbellReg	MUnit.IDR
#define OutboundDoorbellReg	MUnit.ODR

struct rx_registers {
	struct rx_mu_registers		MUnit;		// 1300h - 1334h
	u32				reserved1[6];	// 1338h - 134ch
	struct rx_inbound		IndexRegs;
};

#define rx_readb(AEP, CSR)		readb(&((AEP)->regs.rx->CSR))
#define rx_readl(AEP, CSR)		readl(&((AEP)->regs.rx->CSR))
#define rx_writeb(AEP, CSR, value)	writeb(value, &((AEP)->regs.rx->CSR))
#define rx_writel(AEP, CSR, value)	writel(value, &((AEP)->regs.rx->CSR))

struct fib;

typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);

struct aac_fib_context {
	s16	 		type;		// used for verification of structure	
	s16	 		size;
	u32			jiffies;	// used for cleanup
	struct list_head	next;		// used to link context's into a linked list
	struct semaphore 	wait_sem;	// this is used to wait for the next fib to arrive.
	int			wait;		// Set to true when thread is in WaitForSingleObject
	unsigned long		count;		// total number of FIBs on FibList
	struct list_head	fibs;
};

#define MAXIMUM_NUM_CONTAINERS	64		// 4 Luns * 16 Targets
#define MAXIMUM_NUM_ADAPTERS	8

struct fsa_scsi_hba {
	unsigned long		size[MAXIMUM_NUM_CONTAINERS];
	unsigned long		type[MAXIMUM_NUM_CONTAINERS];
	unsigned char		valid[MAXIMUM_NUM_CONTAINERS];
	unsigned char		ro[MAXIMUM_NUM_CONTAINERS];
	unsigned char		locked[MAXIMUM_NUM_CONTAINERS];
	unsigned char		deleted[MAXIMUM_NUM_CONTAINERS];
	long			devno[MAXIMUM_NUM_CONTAINERS];
};

struct fib {
	void			*next;	/* this is used by the allocator */
	s16			type;
	s16			size;
	/*
	 *	The Adapter that this I/O is destined for.
	 */
	struct aac_dev 		*dev;
	u64			logicaladdr;	/* 64 bit */
	/*
	 *	This is the event the sendfib routine will wait on if the
	 *	caller did not pass one and this is synch io.
	 */
	struct semaphore 	event_wait;
	spinlock_t		event_lock;

	unsigned long		done;	/* gets set to 1 when fib is complete */
	fib_callback 		callback;
	void 			*callback_data;
	unsigned long		flags;
	/*
	 *	The following is used to put this fib context onto the 
	 *	Outstanding I/O queue.
	 */
	struct list_head	queue;

	void 			*data;
	struct hw_fib		*fib;		/* Actual shared object */
};

struct aac_dev
{
	struct aac_dev		*next;
	const char		*name;
	int			id;

	u16			irq_mask;
	/*
	 *	Map for 128 fib objects (64k)
	 */	
	dma_addr_t		hw_fib_pa;
	struct hw_fib		*hw_fib_va;
	/*
	 *	Fib Headers
	 */
	struct fib		fibs[AAC_NUM_FIB];
	struct fib		*free_fib;
	struct fib		*timeout_fib;
	spinlock_t		fib_lock;
	
	struct aac_queue_block *queues;
	/*
	 *	The user API will use an IOCTL to register itself to receive
	 *	FIBs from the adapter.  The following list is used to keep
	 *	track of all the threads that have requested these FIBs.  The
	 *	mutex is used to synchronize access to all data associated 
	 *	with the adapter fibs.
	 */
	struct list_head	fib_list;

	struct adapter_ops	a_ops;
	unsigned long		fsrev;		/* Main driver's revision number */
	
	struct aac_init		*init;		/* Holds initialization info to communicate with adapter */
	void *			init_pa; 	/* Holds physical address of the init struct */
	
	struct pci_dev		*pdev;		/* Our PCI interface */
	void *			printfbuf;	/* pointer to buffer used for printf's from the adapter */
	void *			comm_addr;	/* Base address of Comm area */
	dma_addr_t		comm_phys;	/* Physical Address of Comm area */
	size_t			comm_size;

	struct Scsi_Host	*scsi_host_ptr;
	struct fsa_scsi_hba	fsa_dev;
	int			thread_pid;
	int			cardtype;
	
	/*
	 *	The following is the device specific extension.
	 */
	union
	{
		struct sa_registers *sa;
		struct rx_registers *rx;
	} regs;
	/*
	 *	The following is the number of the individual adapter
	 */
	long			devnum;
	int			aif_thread;
	struct completion	aif_completion;
};

#define AllocateAndMapFibSpace(dev, MapFibContext) \
	dev->a_ops.AllocateAndMapFibSpace(dev, MapFibContext)

#define UnmapAndFreeFibSpace(dev, MapFibContext) \
	dev->a_ops.UnmapAndFreeFibSpace(dev, MapFibContext)

#define aac_adapter_interrupt(dev) \
	dev->a_ops.adapter_interrupt(dev)

#define aac_adapter_notify(dev, event) \
	dev->a_ops.adapter_notify(dev, event)

#define aac_adapter_enable_int(dev, event) \
	dev->a_ops.adapter_enable_int(dev, event)

#define aac_adapter_disable_int(dev, event) \
	dev->a_ops.adapter_disable_int(dev, event)



#define FIB_CONTEXT_FLAG_TIMED_OUT		(0x00000001)

/*
 *	Define the command values
 */
 
#define		Null			0
#define 	GetAttributes		1
#define 	SetAttributes		2
#define 	Lookup			3
#define 	ReadLink		4
#define 	Read			5
#define 	Write			6
#define		Create			7
#define		MakeDirectory		8
#define		SymbolicLink		9
#define		MakeNode		10
#define		Removex			11
#define		RemoveDirectoryx	12
#define		Rename			13
#define		Link			14
#define		ReadDirectory		15
#define		ReadDirectoryPlus	16
#define		FileSystemStatus	17
#define		FileSystemInfo		18
#define		PathConfigure		19
#define		Commit			20
#define		Mount			21
#define		UnMount			22
#define		Newfs			23
#define		FsCheck			24
#define		FsSync			25
#define		SimReadWrite		26
#define		SetFileSystemStatus	27
#define		BlockRead		28
#define		BlockWrite		29
#define		NvramIoctl		30
#define		FsSyncWait		31
#define		ClearArchiveBit		32
#define		SetAcl			33
#define		GetAcl			34
#define		AssignAcl		35
#define		FaultInsertion		36	/* Fault Insertion Command */
#define		CrazyCache		37	/* Crazycache */

#define		MAX_FSACOMMAND_NUM	38


/*
 *	Define the status returns. These are very unixlike although
 *	most are not in fact used
 */

#define		ST_OK		0
#define		ST_PERM		1
#define		ST_NOENT	2
#define		ST_IO		5
#define		ST_NXIO		6
#define		ST_E2BIG	7
#define		ST_ACCES	13
#define		ST_EXIST	17
#define		ST_XDEV		18
#define		ST_NODEV	19
#define		ST_NOTDIR	20
#define		ST_ISDIR	21
#define		ST_INVAL	22
#define		ST_FBIG		27