mga_drv.h

linux和2410结合开发 用他可以生成2410所需的zImage文件

/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
 * Created: Mon Dec 13 01:50:01 1999 by [e-mail]
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Gareth Hughes <[e-mail]>
 */

#ifndef __MGA_DRV_H__
#define __MGA_DRV_H__

typedef struct drm_mga_primary_buffer {
	u8 *start;
	u8 *end;
	int size;

	u32 tail;
	int space;
	volatile int wrapped;

	volatile u32 *status;

	u32 last_flush;
	u32 last_wrap;

	u32 high_mark;

	spinlock_t list_lock;
} drm_mga_primary_buffer_t;

typedef struct drm_mga_freelist {
   	struct drm_mga_freelist *next;
   	struct drm_mga_freelist *prev;
	drm_mga_age_t age;
   	drm_buf_t *buf;
} drm_mga_freelist_t;

typedef struct {
   	drm_mga_freelist_t *list_entry;
	int discard;
	int dispatched;
} drm_mga_buf_priv_t;

typedef struct drm_mga_private {
	drm_mga_primary_buffer_t prim;
	drm_mga_sarea_t *sarea_priv;

   	drm_mga_freelist_t *head;
   	drm_mga_freelist_t *tail;

	unsigned int warp_pipe;
	unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];

	int chipset;
	int usec_timeout;

	u32 clear_cmd;
	u32 maccess;

	unsigned int fb_cpp;
	unsigned int front_offset;
	unsigned int front_pitch;
	unsigned int back_offset;
	unsigned int back_pitch;

	unsigned int depth_cpp;
	unsigned int depth_offset;
	unsigned int depth_pitch;

	unsigned int texture_offset;
	unsigned int texture_size;

	drm_map_t *sarea;
	drm_map_t *fb;
	drm_map_t *mmio;
	drm_map_t *status;
	drm_map_t *warp;
	drm_map_t *primary;
	drm_map_t *buffers;
	drm_map_t *agp_textures;
} drm_mga_private_t;

				/* mga_dma.c */
extern int mga_dma_init( struct inode *inode, struct file *filp,
			 unsigned int cmd, unsigned long arg );
extern int mga_dma_flush( struct inode *inode, struct file *filp,
			  unsigned int cmd, unsigned long arg );
extern int mga_dma_reset( struct inode *inode, struct file *filp,
			  unsigned int cmd, unsigned long arg );
extern int mga_dma_buffers( struct inode *inode, struct file *filp,
			    unsigned int cmd, unsigned long arg );

extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
extern int mga_do_dma_idle( drm_mga_private_t *dev_priv );
extern int mga_do_dma_reset( drm_mga_private_t *dev_priv );
extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
extern int mga_do_cleanup_dma( drm_device_t *dev );

extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );

extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );

				/* mga_state.c */
extern int  mga_dma_clear( struct inode *inode, struct file *filp,
			   unsigned int cmd, unsigned long arg );
extern int  mga_dma_swap( struct inode *inode, struct file *filp,
			  unsigned int cmd, unsigned long arg );
extern int  mga_dma_vertex( struct inode *inode, struct file *filp,
			    unsigned int cmd, unsigned long arg );
extern int  mga_dma_indices( struct inode *inode, struct file *filp,
			     unsigned int cmd, unsigned long arg );
extern int  mga_dma_iload( struct inode *inode, struct file *filp,
			   unsigned int cmd, unsigned long arg );
extern int  mga_dma_blit( struct inode *inode, struct file *filp,
			  unsigned int cmd, unsigned long arg );

				/* mga_warp.c */
extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
extern int mga_warp_init( drm_mga_private_t *dev_priv );

#define mga_flush_write_combine()	mb()


#define MGA_BASE( reg )		((unsigned long)(dev_priv->mmio->handle))
#define MGA_ADDR( reg )		(MGA_BASE(reg) + reg)

#define MGA_DEREF( reg )	*(volatile u32 *)MGA_ADDR( reg )
#define MGA_DEREF8( reg )	*(volatile u8 *)MGA_ADDR( reg )

#ifdef __alpha__
#define MGA_READ( reg )		(_MGA_READ((u32 *)MGA_ADDR(reg)))
#define MGA_WRITE( reg, val )	do { wmb(); MGA_DEREF( reg ) = val; } while (0)
#define MGA_WRITE8( reg, val )  do { wmb(); MGA_DEREF8( reg ) = val; } while (0)

static inline u32 _MGA_READ(u32 *addr)
{
	mb();
	return *(volatile u32 *)addr;
}

#else
#define MGA_READ( reg )		MGA_DEREF( reg )
#define MGA_WRITE( reg, val )	do { MGA_DEREF( reg ) = val; } while (0)
#define MGA_WRITE8( reg, val )  do { MGA_DEREF8( reg ) = val; } while (0)
#endif

#define DWGREG0 	0x1c00
#define DWGREG0_END 	0x1dff
#define DWGREG1		0x2c00
#define DWGREG1_END	0x2dff

#define ISREG0(r)	(r >= DWGREG0 && r <= DWGREG0_END)
#define DMAREG0(r)	(u8)((r - DWGREG0) >> 2)
#define DMAREG1(r)	(u8)(((r - DWGREG1) >> 2) | 0x80)
#define DMAREG(r)	(ISREG0(r) ? DMAREG0(r) : DMAREG1(r))



/* ================================================================
 * Helper macross...
 */

#define MGA_EMIT_STATE( dev_priv, dirty )				\
do {									\
	if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) {			\
		if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {	\
			mga_g400_emit_state( dev_priv );		\
		} else {						\
			mga_g200_emit_state( dev_priv );		\
		}							\
	}								\
} while (0)

#define LOCK_TEST_WITH_RETURN( dev )					\
do {									\
	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||		\
	     dev->lock.pid != current->pid ) {				\
		DRM_ERROR( "%s called without lock held\n",		\
			   __FUNCTION__ );				\
		return -EINVAL;						\
	}								\
} while (0)

#define WRAP_TEST_WITH_RETURN( dev_priv )				\
do {									\
	if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {			\
		if ( mga_is_idle( dev_priv ) ) {			\
			mga_do_dma_wrap_end( dev_priv );		\
		} else if ( dev_priv->prim.space <			\
			    dev_priv->prim.high_mark ) {		\
			if ( MGA_DMA_DEBUG )				\
				DRM_INFO( __FUNCTION__": wrap...\n" );	\
			return -EBUSY;					\
		}							\
	}								\
} while (0)

#define WRAP_WAIT_WITH_RETURN( dev_priv )				\
do {									\
	if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {			\
		if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {		\
			if ( MGA_DMA_DEBUG )				\
				DRM_INFO( __FUNCTION__": wrap...\n" );	\
			return -EBUSY;					\
		}							\
		mga_do_dma_wrap_end( dev_priv );			\
	}								\
} while (0)


/* ================================================================
 * Primary DMA command stream
 */

#define MGA_VERBOSE	0

#define DMA_LOCALS	unsigned int write; volatile u8 *prim;

#define DMA_BLOCK_SIZE	(5 * sizeof(u32))

#define BEGIN_DMA( n )							\
do {									\
	if ( MGA_VERBOSE ) {						\
		DRM_INFO( "BEGIN_DMA( %d ) in %s\n",			\
			  (n), __FUNCTION__ );				\
		DRM_INFO( "   space=0x%x req=0x%x\n",			\
			  dev_priv->prim.space, (n) * DMA_BLOCK_SIZE );	\
	}								\
	prim = dev_priv->prim.start;					\
	write = dev_priv->prim.tail;					\
} while (0)

#define BEGIN_DMA_WRAP()						\
do {									\
	if ( MGA_VERBOSE ) {						\
		DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ );	\
		DRM_INFO( "   space=0x%x\n", dev_priv->prim.space );	\
	}								\
	prim = dev_priv->prim.start;					\
	write = dev_priv->prim.tail;					\
} while (0)

#define ADVANCE_DMA()							\
do {									\
	dev_priv->prim.tail = write;					\
	if ( MGA_VERBOSE ) {						\
		DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n",	\
			  write, dev_priv->prim.space );		\
	}								\
} while (0)

#define FLUSH_DMA()							\
do {									\
	if ( 0 ) {							\
		DRM_INFO( __FUNCTION__ ":\n" );				\
		DRM_INFO( "   tail=0x%06x head=0x%06lx\n",		\
			  dev_priv->prim.tail,				\
			  MGA_READ( MGA_PRIMADDRESS ) -			\
			  dev_priv->primary->offset );			\
	}								\
	if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) {		\
		if ( dev_priv->prim.space <				\
		     dev_priv->prim.high_mark ) {			\
			mga_do_dma_wrap_start( dev_priv );		\
		} else {						\
			mga_do_dma_flush( dev_priv );			\
		}							\
	}								\
} while (0)

/* Never use this, always use DMA_BLOCK(...) for primary DMA output.
 */
#define DMA_WRITE( offset, val )					\
do {									\
	if ( MGA_VERBOSE ) {						\
		DRM_INFO( "   DMA_WRITE( 0x%08x ) at 0x%04x\n",		\
			  (u32)(val), write + (offset) * sizeof(u32) );	\
	}								\
	*(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val;	\
} while (0)

#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 )	\
do {									\
	DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) |				\
		       (DMAREG( reg1 ) << 8) |				\
		       (DMAREG( reg2 ) << 16) |				\
		       (DMAREG( reg3 ) << 24)) );			\
	DMA_WRITE( 1, val0 );						\
	DMA_WRITE( 2, val1 );						\
	DMA_WRITE( 3, val2 );						\
	DMA_WRITE( 4, val3 );						\
	write += DMA_BLOCK_SIZE;					\
} while (0)


/* Buffer aging via primary DMA stream head pointer.
 */