i82092.c

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} /* i82092aa_register_callback */
                                        
static int i82092aa_inquire_socket(unsigned int sock, socket_cap_t *cap)
{
	enter("i82092aa_inquire_socket");
	*cap = sockets[sock].cap;
	leave("i82092aa_inquire_socket");
	return 0;
} /* i82092aa_inquire_socket */


static int i82092aa_get_status(unsigned int sock, u_int *value)
{
	unsigned int status;
	
	enter("i82092aa_get_status");
	
	status = indirect_read(sock,I365_STATUS); /* Interface Status Register */
	*value = 0;
	
	if ((status & I365_CS_DETECT) == I365_CS_DETECT) {
		*value |= SS_DETECT;
	}
		
	/* IO cards have a different meaning of bits 0,1 */
	/* Also notice the inverse-logic on the bits */
	 if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD)	{
	 	/* IO card */
	 	if (!(status & I365_CS_STSCHG))
	 		*value |= SS_STSCHG;
	 } else { /* non I/O card */
	 	if (!(status & I365_CS_BVD1))
	 		*value |= SS_BATDEAD;
	 	if (!(status & I365_CS_BVD2))
	 		*value |= SS_BATWARN;
	 		
	 }
	 
	 if (status & I365_CS_WRPROT)
	 	(*value) |= SS_WRPROT;	/* card is write protected */
	 
	 if (status & I365_CS_READY)
	 	(*value) |= SS_READY;    /* card is not busy */
	 	
	 if (status & I365_CS_POWERON)
	 	(*value) |= SS_POWERON;  /* power is applied to the card */


	leave("i82092aa_get_status");
	return 0;
}


static int i82092aa_get_socket(unsigned int sock, socket_state_t *state) 
{
	unsigned char reg,vcc,vpp;
	
	enter("i82092aa_get_socket");
	state->flags    = 0;
	state->Vcc      = 0;
	state->Vpp      = 0;
	state->io_irq   = 0;
	state->csc_mask = 0;

	/* First the power status of the socket */
	reg = indirect_read(sock,I365_POWER); /* PCTRL - Power Control Register */

	if (reg & I365_PWR_AUTO)
		state->flags |= SS_PWR_AUTO;  /* Automatic Power Switch */
		
	if (reg & I365_PWR_OUT)
		state->flags |= SS_OUTPUT_ENA; /* Output signals are enabled */
		
	vcc = reg & I365_VCC_MASK;    vpp = reg & I365_VPP1_MASK;
	
	if (reg & I365_VCC_5V) { /* Can still be 3.3V, in this case the Vcc value will be overwritten later */
		state->Vcc = 50;
		
		if (vpp == I365_VPP1_5V)
			state->Vpp = 50;
		if (vpp == I365_VPP1_12V)
			state->Vpp = 120;
			
	}
	
	if ((reg & I365_VCC_3V)==I365_VCC_3V)
		state->Vcc = 33;
	
	
	/* Now the IO card, RESET flags and IO interrupt */
	
	reg = indirect_read(sock, I365_INTCTL); /* IGENC, Interrupt and General Control */
	
	if ((reg & I365_PC_RESET)==0)
		state->flags |= SS_RESET;
	if (reg & I365_PC_IOCARD) 
		state->flags |= SS_IOCARD; /* This is an IO card */
	
	/* Set the IRQ number */
	if (sockets[sock].dev!=NULL)
		state->io_irq = sockets[sock].dev->irq;
	
	/* Card status change */
	reg = indirect_read(sock, I365_CSCINT); /* CSCICR, Card Status Change Interrupt Configuration */
	
	if (reg & I365_CSC_DETECT) 
		state->csc_mask |= SS_DETECT; /* Card detect is enabled */
	
	if (state->flags & SS_IOCARD) {/* IO Cards behave different */
		if (reg & I365_CSC_STSCHG)
			state->csc_mask |= SS_STSCHG;
	} else {
		if (reg & I365_CSC_BVD1) 
			state->csc_mask |= SS_BATDEAD;
		if (reg & I365_CSC_BVD2) 
			state->csc_mask |= SS_BATWARN;
		if (reg & I365_CSC_READY) 
			state->csc_mask |= SS_READY;
	}
		
	leave("i82092aa_get_socket");
	return 0;
}

static int i82092aa_set_socket(unsigned int sock, socket_state_t *state) 
{
	unsigned char reg;
	
	enter("i82092aa_set_socket");
	
	/* First, set the global controller options */
	
	set_bridge_state(sock);
	
	/* Values for the IGENC register */
	
	reg = 0;
	if (!(state->flags & SS_RESET)) 	/* The reset bit has "inverse" logic */
		reg = reg | I365_PC_RESET;  
	if (state->flags & SS_IOCARD) 
		reg = reg | I365_PC_IOCARD;
		
	indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */
	
	/* Power registers */
	
	reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */
	
	if (state->flags & SS_PWR_AUTO) {
		printk("Auto power\n");
		reg |= I365_PWR_AUTO;	/* automatic power mngmnt */
	}
	if (state->flags & SS_OUTPUT_ENA) {
		printk("Power Enabled \n");
		reg |= I365_PWR_OUT;	/* enable power */
	}
	
	switch (state->Vcc) {
		case 0:	
			break;
		case 50: 
			printk("setting voltage to Vcc to 5V on socket %i\n",sock);
			reg |= I365_VCC_5V;
			break;
		default:
			printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc);
			leave("i82092aa_set_socket");
			return -EINVAL;
	}
	
	
	switch (state->Vpp) {
		case 0:	
			printk("not setting Vpp on socket %i\n",sock);
			break;
		case 50: 
			printk("setting Vpp to 5.0 for socket %i\n",sock);
			reg |= I365_VPP1_5V | I365_VPP2_5V;
			break;
		case 120: 
			printk("setting Vpp to 12.0\n");
			reg |= I365_VPP1_12V | I365_VPP2_12V;
			break;
		default:
			printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc);
			leave("i82092aa_set_socket");
			return -EINVAL;
	}
	
	if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */
		indirect_write(sock,I365_POWER,reg);
		
	/* Enable specific interrupt events */
	
	reg = 0x00;
	if (state->csc_mask & SS_DETECT) {
		reg |= I365_CSC_DETECT;
	}
	if (state->flags & SS_IOCARD) {
		if (state->csc_mask & SS_STSCHG)
			reg |= I365_CSC_STSCHG;
	} else {
		if (state->csc_mask & SS_BATDEAD) 
			reg |= I365_CSC_BVD1;
		if (state->csc_mask & SS_BATWARN) 
			reg |= I365_CSC_BVD2;
		if (state->csc_mask & SS_READY) 
			reg |= I365_CSC_READY; 
		                        
	}
	
	/* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/
	
	indirect_write(sock,I365_CSCINT,reg);
	(void)indirect_read(sock,I365_CSC);

	leave("i82092aa_set_socket");
	return 0;
}

static int i82092aa_get_io_map(unsigned int sock, struct pccard_io_map *io)
{
	unsigned char map, ioctl, addr;
	
	enter("i82092aa_get_io_map");
	map = io->map;
	if (map > 1) {
		leave("i82092aa_get_io_map with -EINVAL");
		return -EINVAL;
	}
	
	/* FIXME: How does this fit in with the PCI resource (re)allocation */
	io->start = indirect_read16(sock, I365_IO(map)+I365_W_START);
	io->stop  = indirect_read16(sock, I365_IO(map)+I365_W_START);
	
	ioctl = indirect_read(sock,I365_IOCTL); /* IOCREG: I/O Control Register */
	addr  = indirect_read(sock,I365_ADDRWIN); /* */
	
	io->speed = to_ns(ioctl & I365_IOCTL_WAIT(map)) ? 1 : 0; /* check this out later */
	io->flags = 0;
	
	if (addr & I365_IOCTL_16BIT(map))
		io->flags |= MAP_AUTOSZ;
		
	leave("i82092aa_get_io_map");
	return 0;
}

static int i82092aa_set_io_map(unsigned sock, struct pccard_io_map *io)
{
	unsigned char map, ioctl;
	
	enter("i82092aa_set_io_map");
	
	map = io->map;
	
	/* Check error conditions */	
	if (map > 1) {
		leave("i82092aa_set_io_map with invalid map");
		return -EINVAL;
	}
	if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){
		leave("i82092aa_set_io_map with invalid io");
		return -EINVAL;
	}

	/* Turn off the window before changing anything */ 
	if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map))
		indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map));

/*	printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop);  */
	
	/* write the new values */
	indirect_write16(sock,I365_IO(map)+I365_W_START,io->start);            	
	indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop);            	
	            	
	ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map);
	
	if (io->flags & (MAP_16BIT|MAP_AUTOSZ))
		ioctl |= I365_IOCTL_16BIT(map);
		
	indirect_write(sock,I365_IOCTL,ioctl);
	
	/* Turn the window back on if needed */
	if (io->flags & MAP_ACTIVE)
		indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map));
			
	leave("i82092aa_set_io_map");	
	return 0;
}

static int i82092aa_get_mem_map(unsigned sock, struct pccard_mem_map *mem)
{
	unsigned short base, i;
	unsigned char map, addr;
	
	enter("i82092aa_get_mem_map");
	
	mem->flags = 0;
	mem->speed = 0;
	map = mem->map;
	if (map > 4) {
		leave("i82092aa_get_mem_map: -EINVAL");
		return -EINVAL;
	}
	
	addr = indirect_read(sock, I365_ADDRWIN);
		
	if (addr & I365_ENA_MEM(map))
		mem->flags |= MAP_ACTIVE;		/* yes this mapping is active */
	
	base = I365_MEM(map); 
	
	/* Find the start address - this register also has mapping info */
	
	i = indirect_read16(sock,base+I365_W_START);
	if (i & I365_MEM_16BIT)
		mem->flags |= MAP_16BIT;
	if (i & I365_MEM_0WS)
		mem->flags |= MAP_0WS;
	
	mem->sys_start = ((unsigned long)(i & 0x0fff) << 12);
	
	/* Find the end address - this register also has speed info */
	i = indirect_read16(sock,base+I365_W_STOP);
	if (i & I365_MEM_WS0)
		mem->speed = 1;
	if (i & I365_MEM_WS1)
		mem->speed += 2;
	mem->speed = to_ns(mem->speed);
	mem->sys_stop = ( (unsigned long)(i & 0x0fff) << 12) + 0x0fff;
	
	/* Find the card start address, also some more MAP attributes */
	
	i = indirect_read16(sock, base+I365_W_OFF);
	if (i & I365_MEM_WRPROT)
		mem->flags |= MAP_WRPROT;
	if (i & I365_MEM_REG)
		mem->flags |= MAP_ATTRIB;
	mem->card_start = ( (unsigned long)(i & 0x3fff)<12) + mem->sys_start;
	mem->card_start &=  0x3ffffff;
	
	printk("Card %i is from %lx to %lx \n",sock,mem->sys_start,mem->sys_stop);
	
	leave("i82092aa_get_mem_map");
	return 0;
	
}

static int i82092aa_set_mem_map(unsigned sock, struct pccard_mem_map *mem)
{
	unsigned short base, i;
	unsigned char map;
	
	enter("i82092aa_set_mem_map");
	
	map = mem->map;
	if (map > 4) {
		leave("i82092aa_set_mem_map: invalid map");
		return -EINVAL;
	}
	
	
	if ( (mem->card_start > 0x3ffffff) || (mem->sys_start > mem->sys_stop) ||
	     (mem->speed > 1000) ) {
		leave("i82092aa_set_mem_map: invalid address / speed");
		printk("invalid mem map for socket %i : %lx to %lx with a start of %x \n",sock,mem->sys_start, mem->sys_stop, mem->card_start);
		return -EINVAL;
	}
	
	/* Turn off the window before changing anything */
	if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
	              indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
	                 
	                 
/* 	printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, mem->sys_start,mem->sys_stop,sock,mem->speed,mem->flags & MAP_ACTIVE);  */

	/* write the start address */
	base = I365_MEM(map);
	i = (mem->sys_start >> 12) & 0x0fff;
	if (mem->flags & MAP_16BIT) 
		i |= I365_MEM_16BIT;
	if (mem->flags & MAP_0WS)
		i |= I365_MEM_0WS;	
	indirect_write16(sock,base+I365_W_START,i);
		               
	/* write the stop address */
	
	i= (mem->sys_stop >> 12) & 0x0fff;
	switch (to_cycles(mem->speed)) {
		case 0:
			break;
		case 1:
			i |= I365_MEM_WS0;
			break;
		case 2:
			i |= I365_MEM_WS1;
			break;
		default:
			i |= I365_MEM_WS1 | I365_MEM_WS0;
			break;
	}
	
	indirect_write16(sock,base+I365_W_STOP,i);
	
	/* card start */
	
	i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
	if (mem->flags & MAP_WRPROT)
		i |= I365_MEM_WRPROT;
	if (mem->flags & MAP_ATTRIB) {
/*		printk("requesting attribute memory for socket %i\n",sock);*/
		i |= I365_MEM_REG;
	} else {
/*		printk("requesting normal memory for socket %i\n",sock);*/
	}
	indirect_write16(sock,base+I365_W_OFF,i);
	
	/* Enable the window if necessary */
	if (mem->flags & MAP_ACTIVE)
		indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
	            
	leave("i82092aa_set_mem_map");
	return 0;
}

static void i82092aa_proc_setup(unsigned int sock, struct proc_dir_entry *base)
{
	
}
/* Module stuff */

static int i82092aa_module_init(void)
{
	enter("i82092aa_module_init");
	pci_register_driver(&i82092aa_pci_drv);
	leave("i82092aa_module_init");
	return 0;
}

static void i82092aa_module_exit(void)
{
	enter("i82092aa_module_exit");
	pci_unregister_driver(&i82092aa_pci_drv);
	unregister_ss_entry(&i82092aa_operations);
	if (sockets[0].io_base>0)
			 release_region(sockets[0].io_base, 2);
	leave("i82092aa_module_exit");
}

module_init(i82092aa_module_init);
module_exit(i82092aa_module_exit);