rme96xx.c

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/* (C) 2000 Guenter Geiger <[e-mail]>
   with copy/pastes from the driver of Winfried Ritsch <[e-mail]>
   based on es1370.c



   *  10 Jan 2001: 0.1 initial version
   *  19 Jan 2001: 0.2 fixed bug in select()
   *  27 Apr 2001: 0.3 more than one card usable
   *  11 May 2001: 0.4 fixed for SMP, included into kernel source tree
   *  17 May 2001: 0.5 draining code didn't work on new cards
   *  18 May 2001: 0.6 remove synchronize_irq() call 

TODO:
   - test more than one card --- done
   - check for pci IOREGION (see es1370) in rme96xx_probe ??
   - error detection
   - mmap interface
   - mixer mmap interface
   - mixer ioctl
   - get rid of noise upon first open (why ??)
   - allow multiple open(at least for read)
   - allow multiple open for non overlapping regions
   - recheck the multiple devices part (offsets of different devices, etc)
   - do decent draining in _release --- done
   - SMP support
*/

#ifndef RMEVERSION
#define RMEVERSION "0.6"
#endif

#include <linux/version.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/sched.h>
#include <linux/sound.h>
#include <linux/soundcard.h>
#include <linux/pci.h>
#include <linux/smp_lock.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <asm/dma.h>
#include <linux/init.h>
#include <linux/poll.h>
#include "rme96xx.h"

#define NR_DEVICE 2

static int devices = 1;
MODULE_PARM(devices, "1-" __MODULE_STRING(NR_DEVICE) "i");
MODULE_PARM_DESC(devices, "number of dsp devices allocated by the driver");


MODULE_AUTHOR("Guenter Geiger, [e-mail]");
MODULE_DESCRIPTION("RME9652/36 \"Hammerfall\" Driver");
MODULE_LICENSE("GPL");


#ifdef DEBUG
#define DBG(x) printk("RME_DEBUG:");x
#define COMM(x) printk("RME_COMM: " x "\n");
#else
#define DBG(x) while (0) {}
#define COMM(x)
#endif

/*-------------------------------------------------------------------------- 
                        Preporcessor Macros and Definitions
 --------------------------------------------------------------------------*/

#define RME96xx_MAGIC 0x6473

/* Registers-Space in offsets from base address with 16MByte size */

#define RME96xx_IO_EXTENT     16l*1024l*1024l
#define RME96xx_CHANNELS_PER_CARD 26

/*                  Write - Register */

/* 0,4,8,12,16,20,24,28 ... hardware init (erasing fifo-pointer intern) */
#define RME96xx_num_of_init_regs   8

#define RME96xx_init_buffer       (0/4)
#define RME96xx_play_buffer       (32/4)  /* pointer to 26x64kBit RAM from mainboard */
#define RME96xx_rec_buffer        (36/4)  /* pointer to 26x64kBit RAM from mainboard */
#define RME96xx_control_register  (64/4)  /* exact meaning see below */
#define RME96xx_irq_clear         (96/4)  /* irq acknowledge */
#define RME96xx_time_code         (100/4) /* if used with alesis adat */
#define RME96xx_thru_base         (128/4) /* 132...228 Thru for 26 channels */
#define RME96xx_thru_channels     RME96xx_CHANNELS_PER_CARD

/*                     Read Register */

#define RME96xx_status_register    0     /* meaning see below */



/* Status Register: */
/* ------------------------------------------------------------------------ */
#define RME96xx_IRQ          0x0000001 /* IRQ is High if not reset by RMExx_irq_clear */
#define RME96xx_lock_2       0x0000002 /* ADAT 3-PLL: 1=locked, 0=unlocked */
#define RME96xx_lock_1       0x0000004 /* ADAT 2-PLL: 1=locked, 0=unlocked */
#define RME96xx_lock_0       0x0000008 /* ADAT 1-PLL: 1=locked, 0=unlocked */

#define RME96xx_fs48         0x0000010 /* sample rate 0 ...44.1/88.2,  1 ... 48/96 Khz */
#define RME96xx_wsel_rd      0x0000020 /* if Word-Clock is used and valid then 1 */
#define RME96xx_buf_pos1     0x0000040 /* Bit 6..15 : Position of buffer-pointer in 64Bytes-blocks */
#define RME96xx_buf_pos2     0x0000080 /* resolution +/- 1 64Byte/block (since 64Bytes bursts) */
 
#define RME96xx_buf_pos3     0x0000100 /* 10 bits = 1024 values */
#define RME96xx_buf_pos4     0x0000200 /* if we mask off the first 6 bits, we can take the status */
#define RME96xx_buf_pos5     0x0000400 /* register as sample counter in the hardware buffer */
#define RME96xx_buf_pos6     0x0000800 

#define RME96xx_buf_pos7     0x0001000 
#define RME96xx_buf_pos8     0x0002000 
#define RME96xx_buf_pos9     0x0004000
#define RME96xx_buf_pos10    0x0008000 

#define RME96xx_sync_2       0x0010000 /* if ADAT-IN3 synced to system clock */
#define RME96xx_sync_1       0x0020000 /* if ADAT-IN2 synced to system clock */
#define RME96xx_sync_0       0x0040000 /* if ADAT-IN1 synced to system clock */
#define RME96xx_DS_rd        0x0080000 /* 1=Double Speed, 0=Normal Speed */

#define RME96xx_tc_busy      0x0100000 /* 1=time-code copy in progress (960ms) */
#define RME96xx_tc_out       0x0200000 /* time-code out bit */
#define RME96xx_F_0          0x0400000 /*  000=64kHz, 100=88.2kHz, 011=96kHz  */
#define RME96xx_F_1          0x0800000 /*  111=32kHz, 110=44.1kHz, 101=48kHz, */

#define RME96xx_F_2          0x1000000 /*  od external Crystal Chip if ERF=1*/
#define RME96xx_ERF          0x2000000 /* Error-Flag of SDPIF Receiver (1=No Lock)*/
#define RME96xx_buffer_id    0x4000000 /* toggles by each interrupt on rec/play */
#define RME96xx_tc_valid     0x8000000 /* 1 = a signal is detected on time-code input */

/* Status Register Fields */

#define RME96xx_lock            (RME96xx_lock_0|RME96xx_lock_1|RME96xx_lock_2)
#define RME96xx_buf_pos          0x000FFC0 
#define RME96xx_sync            (RME96xx_sync_0|RME96xx_sync_1|RME96xx_sync_2)
#define RME96xx_F               (RME96xx_F_0|RME96xx_F_1|RME96xx_F_2)



/* Control-Register: */			    
/*--------------------------------------------------------------------------------*/

#define RME96xx_start_bit	   0x0001    /* start record/play */
#define RME96xx_latency0	   0x0002    /* Bit 0 -  Buffer size or latency */
#define RME96xx_latency1	   0x0004    /* Bit 1 - Buffer size or latency */
#define RME96xx_latency2	   0x0008    /* Bit 2 - Buffer size or latency */

#define RME96xx_Master		   0x0010   /* Clock Mode Master=1,Slave/Auto=0 */
#define RME96xx_IE		   0x0020   /* Interupt Enable */
#define RME96xx_freq		   0x0040   /* samplerate 0=44.1/88.2, 1=48/96 kHz*/


#define RME96xx_DS                 0x0100   /* Doule Speed 0=44.1/48, 1=88.2/96 Khz */
#define RME96xx_PRO		   0x0200    /* spdif 0=consumer, 1=professional Mode*/
#define RME96xx_EMP		   0x0400    /* spdif Emphasis 0=None, 1=ON */
#define RME96xx_Dolby		   0x0800    /* spdif Non-audio bit 1=set, 0=unset */

#define RME96xx_opt_out	           0x1000  /* Use 1st optical OUT as SPDIF: 1=yes,0=no */
#define RME96xx_wsel               0x2000  /* use Wordclock as sync (overwrites master)*/
#define RME96xx_inp_0              0x4000  /* SPDIF-IN: 00=optical (ADAT1),     */
#define RME96xx_inp_1              0x8000  /* 01=koaxial (Cinch), 10=Internal CDROM*/

#define RME96xx_SyncRef0           0x10000  /* preferred sync-source in autosync */
#define RME96xx_SyncRef1           0x20000  /* 00=ADAT1,01=ADAT2,10=ADAT3,11=SPDIF */


#define RME96xx_ctrl_init            (RME96xx_latency0 |\
                                     RME96xx_Master |\
                                     RME96xx_inp_1)
                              


/* Control register fields and shortcuts */

#define RME96xx_latency (RME96xx_latency0|RME96xx_latency1|RME96xx_latency2)
#define RME96xx_inp         (RME96xx_inp_0|RME96xx_inp_1)
#define RME96xx_SyncRef    (RME96xx_SyncRef0|RME96xx_SyncRef1)
/* latency = 512Bytes * 2^n, where n is made from Bit3 ... Bit0 */

#define RME96xx_SET_LATENCY(x)   (((x)&0x7)<<1)
#define RME96xx_GET_LATENCY(x)   (((x)>>1)&0x7)
#define RME96xx_SET_inp(x) (((x)&0x3)<<14)
#define RME96xx_GET_inp(x)   (((x)>>14)&0x3)
#define RME96xx_SET_SyncRef(x) (((x)&0x3)<<17)
#define RME96xx_GET_SyncRef(x)   (((x)>>17)&0x3)


/* buffer sizes */
#define RME96xx_BYTES_PER_SAMPLE  4 /* sizeof(u32) */
#define RME_16K 16*1024

#define RME96xx_DMA_MAX_SAMPLES  (RME_16K)
#define RME96xx_DMA_MAX_SIZE     (RME_16K * RME96xx_BYTES_PER_SAMPLE)
#define RME96xx_DMA_MAX_SIZE_ALL (RME96xx_DMA_MAX_SIZE * RME96xx_CHANNELS_PER_CARD)

#define RME96xx_NUM_OF_FRAGMENTS     2
#define RME96xx_FRAGMENT_MAX_SIZE    (RME96xx_DMA_MAX_SIZE/2)
#define RME96xx_FRAGMENT_MAX_SAMPLES (RME96xx_DMA_MAX_SAMPLES/2)
#define RME96xx_MAX_LATENCY       7   /* 16k samples */


#define RME96xx_MAX_DEVS 4 /* we provide some OSS stereodevs */

#define RME_MESS "rme96xx:"
/*------------------------------------------------------------------------ 
                  Types, struct and function declarations 
 ------------------------------------------------------------------------*/


/* --------------------------------------------------------------------- */

static const char invalid_magic[] = KERN_CRIT RME_MESS" invalid magic value\n";

#define VALIDATE_STATE(s)                         \
({                                                \
	if (!(s) || (s)->magic != RME96xx_MAGIC) { \
		printk(invalid_magic);            \
		return -ENXIO;                    \
	}                                         \
})

/* --------------------------------------------------------------------- */


static struct file_operations rme96xx_audio_fops;
static struct file_operations rme96xx_mixer_fops;
static int numcards;

typedef int32_t raw_sample_t;

typedef struct _rme96xx_info {

	/* hardware settings */
	int magic;
	struct pci_dev * pcidev; /* pci_dev structure */
	unsigned long *iobase;	
	unsigned int irq;

	/* list of rme96xx devices */
	struct list_head devs;

	spinlock_t lock;

	u32 *recbuf;             /* memory for rec buffer */
	u32 *playbuf;            /* memory for play buffer */

	u32 control_register;

	u32 thru_bits; /* thru 1=on, 0=off channel 1=Bit1... channel 26= Bit26 */

	int open_count;


	int rate;
	int latency;
	unsigned int fragsize;
	int started;

	int hwptr; /* can be negativ because of pci burst offset  */
	unsigned int hwbufid;  /* set by interrupt, buffer which is written/read now */
	
	struct dmabuf {

		unsigned int format;
		int formatshift;
		int inchannels;       /* number of channels for device */
		int outchannels;       /* number of channels for device */
		int mono; /* if true, we play mono on 2 channels */
		int inoffset; /* which channel is considered the first one */
         	int outoffset;
		
		/* state */
		int opened;               /* open() made */
		int started;              /* first write/read */
		int mmapped;              /* mmap */
		int open_mode;

		struct _rme96xx_info *s;  

		/* pointer to read/write position in buffer */
		unsigned readptr;          
		unsigned writeptr;          

		unsigned error; /* over/underruns cleared on sync again */

		/* waiting and locking */
		wait_queue_head_t wait;
		struct semaphore  open_sem;
		wait_queue_head_t open_wait;

	} dma[RME96xx_MAX_DEVS]; 

	int dspnum[RME96xx_MAX_DEVS];  /* register with sound subsystem */ 
	int mixer;  /* register with sound subsystem */ 
} rme96xx_info;


/* fiddling with the card (first level hardware control) */

inline void rme96xx_set_ctrl(rme96xx_info* s,int mask)
{

	s->control_register|=mask;
	writel(s->control_register,s->iobase + RME96xx_control_register);

}

inline void rme96xx_unset_ctrl(rme96xx_info* s,int mask)
{

	s->control_register&=(~mask);
	writel(s->control_register,s->iobase + RME96xx_control_register);

}



/* the hwbuf in the status register seems to have some jitter, to get rid of
   it, we first only let the numbers grow, to be on the secure side we 
   subtract a certain amount RME96xx_BURSTBYTES from the resulting number */

/* the function returns the hardware pointer in bytes */
#define RME96xx_BURSTBYTES -64  /* bytes by which hwptr could be off */

inline int rme96xx_gethwptr(rme96xx_info* s,int exact)
{
	long flags;
	if (exact) {
		unsigned int hwp;
/* the hwptr seems to be rather unreliable :(, so we don't use it */
		spin_lock_irqsave(&s->lock,flags);
		
		hwp  = readl(s->iobase + RME96xx_status_register) & 0xffc0;
		s->hwptr = (hwp < s->hwptr) ? s->hwptr : hwp;
//		s->hwptr = hwp;

		spin_unlock_irqrestore(&s->lock,flags);
		return (s->hwptr+RME96xx_BURSTBYTES) & ((s->fragsize<<1)-1);
	}
	return (s->hwbufid ? s->fragsize : 0);
}

inline void rme96xx_setlatency(rme96xx_info* s,int l)
{
	s->latency = l;
	s->fragsize = 1<<(8+l);
	rme96xx_unset_ctrl(s,RME96xx_latency);
	rme96xx_set_ctrl(s,RME96xx_SET_LATENCY(l));	
}


static void rme96xx_clearbufs(struct dmabuf* dma)
{
	int i,j;
	unsigned long flags;

	/* clear dmabufs */
	for(i=0;i<devices;i++) {
		for (j=0;j<dma->outchannels + dma->mono;j++)
			memset(&dma->s->playbuf[(dma->outoffset + j)*RME96xx_DMA_MAX_SAMPLES], 
			       0, RME96xx_DMA_MAX_SIZE);
	}
	spin_lock_irqsave(&dma->s->lock,flags);
	dma->writeptr = 0;
	dma->readptr = 0;
	spin_unlock_irqrestore(&dma->s->lock,flags);
}

static int rme96xx_startcard(rme96xx_info *s,int stop)
{
	int i;
	long flags;

	COMM       ("startcard");
	if(s->control_register & RME96xx_IE){
		/* disable interrupt first */
		
		rme96xx_unset_ctrl( s,RME96xx_start_bit );
		udelay(10);
		rme96xx_unset_ctrl( s,RME96xx_IE);
		spin_lock_irqsave(&s->lock,flags); /* timing is critical */
		s->started = 0;
		spin_unlock_irqrestore(&s->lock,flags);
		if (stop) {
		     COMM("Sound card stopped");
		     return 1;
		}
	}
	COMM       ("interupt disabled");
	/* first initialize all pointers on card */
	for(i=0;i<RME96xx_num_of_init_regs;i++){
		writel(0,s->iobase + i);
		udelay(10); /* ?? */
	}
	COMM       ("regs cleaned");

	spin_lock_irqsave(&s->lock,flags); /* timing is critical */
	udelay(10);
	s->started = 1;
	s->hwptr = 0;
	spin_unlock_irqrestore(&s->lock,flags);

	rme96xx_set_ctrl( s, RME96xx_IE | RME96xx_start_bit);


	COMM("Sound card started");
  
	return 1;
}


inline int rme96xx_getospace(struct dmabuf * dma, unsigned int hwp)
{
	int cnt;
	int  swptr;
	unsigned long flags;

	spin_lock_irqsave(&dma->s->lock,flags); 
	swptr = dma->writeptr;
	cnt = (hwp - swptr);
	
	if (cnt < 0) {
	     cnt = ((dma->s->fragsize<<1) - swptr);
	}
	spin_unlock_irqrestore(&dma->s->lock,flags);
	return cnt;
}

inline int rme96xx_getispace(struct dmabuf * dma, unsigned int hwp)
{
	int cnt;
	int  swptr;
	unsigned long flags;

	spin_lock_irqsave(&dma->s->lock,flags); 
	swptr = dma->readptr;
	cnt = (hwp - swptr);
	 
	if (cnt < 0) {
		cnt = ((dma->s->fragsize<<1) - swptr);
	}
	spin_unlock_irqrestore(&dma->s->lock,flags);
	return cnt;
}


inline int rme96xx_copyfromuser(struct dmabuf* dma,const char* buffer,int count,int hop)
{
	int swptr = dma->writeptr;
	switch (dma->format) {
	case AFMT_S32_BLOCKED:
	{
	     char* buf = (char*)buffer;
	     int cnt = count/dma->outchannels;
	     int i;
	     for (i=0;i < dma->outchannels;i++) {
		  char* hwbuf =(char*) &dma->s->playbuf[(dma->outoffset + i)*RME96xx_DMA_MAX_SAMPLES];
		  hwbuf+=swptr;

		  if (copy_from_user(hwbuf,buf, cnt))
		       return -1;
		  buf+=hop;
	     }
	     swptr+=cnt;
	     break;
	}
	case AFMT_S16_LE:
	{
	     int i,j;
	     int cnt = count/dma->outchannels;
	     for (i=0;i < dma->outchannels + dma->mono;i++) {
		     short* sbuf = (short*)buffer + i*(!dma->mono);
		     short* hwbuf =(short*) &dma->s->playbuf[(dma->outoffset + i)*RME96xx_DMA_MAX_SAMPLES];	     
		     hwbuf+=(swptr>>1);
		     for (j=0;j<(cnt>>1);j++) {
			     hwbuf++; /* skip the low 16 bits */
			     __get_user(*hwbuf++,sbuf++);
			     sbuf+=(dma->outchannels-1);
		     }
	     }
	     swptr += (cnt<<1);
	     break;
	}
	default:
	     printk(RME_MESS" unsupported format\n");
	     return -1;
	} /* switch */

	swptr&=((dma->s->fragsize<<1) -1);
	dma->writeptr = swptr;

	return 0;
}

/* The count argument is the number of bytes */
inline int rme96xx_copytouser(struct dmabuf* dma,const char* buffer,int count,int hop)
{
	int swptr = dma->readptr;
	switch (dma->format) {
	case AFMT_S32_BLOCKED:
	{
	     char* buf = (char*)buffer;
	     int cnt = count/dma->inchannels;
	     int i;

	     for (i=0;i < dma->inchannels;i++) {
		  char* hwbuf =(char*) &dma->s->recbuf[(dma->inoffset + i)*RME96xx_DMA_MAX_SAMPLES];
		  hwbuf+=swptr;

		  if (copy_to_user(buf,hwbuf,cnt))
		       return -1;
		  buf+=hop;
	     }
	     swptr+=cnt;
	     break;
	}
	case AFMT_S16_LE: