📄 tcontrol.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tcontrol IS
port (en1: IN STD_LOGIC;
in0: in std_logic_vector(3 downto 0);
in1: in std_logic_vector(3 downto 0);
in2: in std_logic_vector(3 downto 0);
in3: in std_logic_vector(3 downto 0);
in4: in std_logic_vector(3 downto 0);
in5: in std_logic_vector(3 downto 0);
in6: in std_logic_vector(3 downto 0);
out0: out std_logic_vector(7 downto 0);
out1: out std_logic_vector(7 downto 0);
out2: out std_logic_vector(7 downto 0);
out3: out std_logic_vector(7 downto 0);
flage: out std_logic_vector(1 downto 0));
END tcontrol;
ARCHITECTURE behav OF tcontrol IS
signal A0,A1,A2,A3: std_logic_vector(7 downto 0);
signal CQ: std_logic_vector(1 downto 0);
BEGIN
PROCESS(en1)
BEGIN
if en1='1' then
if in6=0 then
if in5=0 then
if in4=0 then
A3(3 downto 0)<=in3;A3(7 downto 4)<="0000";
A2(3 downto 0)<=in2;A2(7 downto 4)<="0000";
A1(3 downto 0)<=in1;A1(7 downto 4)<="0000";
A0(3 downto 0)<=in0;A0(7 downto 4)<="0000";
CQ<="11";
else
A3(3 downto 0)<=in4;A3(7 downto 4)<="0000";
A2(3 downto 0)<=in3;A2(7 downto 4)<="0000";
A1(3 downto 0)<=in2;A1(7 downto 4)<="0000";
A0(3 downto 0)<=in1;A0(7 downto 4)<="0000";
CQ<="10";
end if;
else
A3(3 downto 0)<=in5;A3(7 downto 4)<="0000";
A2(3 downto 0)<=in4;A2(7 downto 4)<="0000";
A1(3 downto 0)<=in3;A1(7 downto 4)<="0000";
A0(3 downto 0)<=in2;A0(7 downto 4)<="0000";
CQ<="01";
end if;
else
A3(3 downto 0)<=in6;A3(7 downto 4)<="0000";
A2(3 downto 0)<=in5;A2(7 downto 4)<="0000";
A1(3 downto 0)<=in4;A1(7 downto 4)<="0000";
A0(3 downto 0)<=in3;A0(7 downto 4)<="0000";
CQ<="00";
end if;
end if;
end PROCESS;
out3<=A3;
out2<=A2;
out1<=A1;
out0<=A0;
flage<=CQ;
end ;
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