chenggong.map.summary

实现由一个4位十进制数码管（含小数点）显示结果

Analysis & Synthesis Status : Successful - Mon May 11 14:21:32 2009
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition
Revision Name : chenggong
Top-level Entity Name : chenggong
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 0
    Dedicated logic registers : 0
Total registers : 0
Total pins : 8
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0