chenggong.map.qmsg

实现由一个4位十进制数码管（含小数点）显示结果

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G3\[6\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G3\[6\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G3\[7\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G3\[7\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G2\[0\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G2\[0\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G2\[1\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G2\[1\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G2\[2\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G2\[2\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G2\[3\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G2\[3\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G2\[4\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G2\[4\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G2\[5\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G2\[5\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G2\[6\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G2\[6\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G2\[7\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G2\[7\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G1\[0\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G1\[0\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G1\[1\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G1\[1\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G1\[2\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G1\[2\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G1\[3\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G1\[3\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G1\[4\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G1\[4\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G1\[5\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G1\[5\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G1\[6\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G1\[6\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "G1\[7\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"G1\[7\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[0\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[0\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[1\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[1\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[2\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[2\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[3\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[3\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[4\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[4\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[5\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[5\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[6\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[6\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[7\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[7\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[0\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[0\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[1\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[1\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[2\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[2\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[3\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[3\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}