chenggong.map.qmsg

实现由一个4位十进制数码管（含小数点）显示结果

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Web Edition " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 11 14:21:25 2009 " "Info: Processing started: Mon May 11 14:21:25 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chenggong -c chenggong " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chenggong -c chenggong" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tcontrol.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tcontrol.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tcontrol-behav " "Info: Found design unit 1: tcontrol-behav" {  } { { "tcontrol.vhd" "" { Text "F:/quartus II/chenggong/tcontrol.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 tcontrol " "Info: Found entity 1: tcontrol" {  } { { "tcontrol.vhd" "" { Text "F:/quartus II/chenggong/tcontrol.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt-behav " "Info: Found design unit 1: cnt-behav" {  } { { "cnt.vhd" "" { Text "F:/quartus II/chenggong/cnt.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt " "Info: Found entity 1: cnt" {  } { { "cnt.vhd" "" { Text "F:/quartus II/chenggong/cnt.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chenggong.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file chenggong.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 chenggong " "Info: Found entity 1: chenggong" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "chenggong " "Info: Elaborating entity \"chenggong\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "out3 " "Warning: Pin \"out3\" is missing source" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 368 -72 104 384 "out3" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0 "" 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "out2 " "Warning: Pin \"out2\" is missing source" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 384 -72 104 400 "out2" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0 "" 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "out1 " "Warning: Pin \"out1\" is missing source" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 400 -72 104 416 "out1" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0 "" 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "out0 " "Warning: Pin \"out0\" is missing source" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 416 -72 104 432 "out0" "" } } } }  } 0 0 "Pin \"%1!s!\" is missing source" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt cnt:inst " "Info: Elaborating entity \"cnt\" for hierarchy \"cnt:inst\"" {  } { { "chenggong.bdf" "inst" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { -8 184 312 88 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "xianshi.vhd 2 1 " "Warning: Using design file xianshi.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 xianshi-behav " "Info: Found design unit 1: xianshi-behav" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 xianshi " "Info: Found entity 1: xianshi" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "xianshi xianshi:inst8 " "Info: Elaborating entity \"xianshi\" for hierarchy \"xianshi:inst8\"" {  } { { "chenggong.bdf" "inst8" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 240 184 336 368 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "C3 xianshi.vhd(17) " "Warning (10036): Verilog HDL or VHDL warning at xianshi.vhd(17): object \"C3\" assigned a value but never read" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "F0 xianshi.vhd(18) " "Warning (10036): Verilog HDL or VHDL warning at xianshi.vhd(18): object \"F0\" assigned a value but never read" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 18 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "A xianshi.vhd(23) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(23): signal \"A\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in0 xianshi.vhd(25) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(25): signal \"in0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in1 xianshi.vhd(26) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(26): signal \"in1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in2 xianshi.vhd(27) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(27): signal \"in2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in3 xianshi.vhd(28) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(28): signal \"in3\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in0 xianshi.vhd(30) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(30): signal \"in0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in1 xianshi.vhd(31) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(31): signal \"in1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in2 xianshi.vhd(32) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(32): signal \"in2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in3 xianshi.vhd(33) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(33): signal \"in3\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in0 xianshi.vhd(35) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(35): signal \"in0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 35 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in1 xianshi.vhd(36) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(36): signal \"in1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 36 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in2 xianshi.vhd(37) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(37): signal \"in2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 37 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in3 xianshi.vhd(38) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(38): signal \"in3\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 38 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "in0 xianshi.vhd(40) " "Warning (10492): VHDL Process Statement warning at xianshi.vhd(40): signal \"in0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 40 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}