prev_cmp_chenggong.map.qmsg

实现由一个4位十进制数码管（含小数点）显示结果

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[3\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[3\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[4\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[4\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[5\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[5\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[6\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[6\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D3\[7\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D3\[7\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[0\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[0\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[1\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[1\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[2\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[2\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[3\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[3\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[4\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[4\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[5\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[5\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[6\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[6\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D2\[7\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D2\[7\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D1\[0\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D1\[0\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D1\[1\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D1\[1\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D1\[2\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D1\[2\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D1\[3\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D1\[3\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D1\[4\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D1\[4\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D1\[5\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D1\[5\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D1\[6\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D1\[6\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D1\[7\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D1\[7\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D0\[0\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D0\[0\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D0\[1\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D0\[1\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D0\[2\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D0\[2\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D0\[3\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D0\[3\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D0\[4\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D0\[4\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D0\[5\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D0\[5\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D0\[6\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D0\[6\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "D0\[7\] xianshi.vhd(20) " "Info (10041): Inferred latch for \"D0\[7\]\" at xianshi.vhd(20)" {  } { { "xianshi.vhd" "" { Text "F:/quartus II/chenggong/xianshi.vhd" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tcontrol tcontrol:inst9 " "Info: Elaborating entity \"tcontrol\" for hierarchy \"tcontrol:inst9\"" {  } { { "chenggong.bdf" "inst9" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 160 392 536 352 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "out3 GND " "Warning (13410): Pin \"out3\" stuck at GND" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 368 -72 104 384 "out3" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "out2 GND " "Warning (13410): Pin \"out2\" stuck at GND" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 384 -72 104 400 "out2" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "out1 GND " "Warning (13410): Pin \"out1\" stuck at GND" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 400 -72 104 416 "out1" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "out0 GND " "Warning (13410): Pin \"out0\" stuck at GND" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 416 -72 104 432 "out0" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "clk " "Warning (15610): No output dependent on input pin \"clk\"" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 16 -16 152 32 "clk" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "en " "Warning (15610): No output dependent on input pin \"en\"" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 32 -16 152 48 "en" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst " "Warning (15610): No output dependent on input pin \"rst\"" {  } { { "chenggong.bdf" "" { Schematic "F:/quartus II/chenggong/chenggong.bdf" { { 504 488 656 520 "rst" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "7 " "Info: Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 84 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 84 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "158 " "Info: Allocated 158 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 14:14:03 2009 " "Info: Processing ended: Mon May 11 14:14:03 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}