chenggong.fit.rpt

实现由一个4位十进制数码管（含小数点）显示结果

Fitter report for chenggong
Mon May 11 14:21:55 2009
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Pad To Core Delay Chain Fanout
 14. Interconnect Usage Summary
 15. I/O Rules Summary
 16. I/O Rules Details
 17. I/O Rules Matrix
 18. Fitter Device Options
 19. Operating Settings and Conditions
 20. Advanced Data - General
 21. Advanced Data - Placement Preparation
 22. Advanced Data - Placement
 23. Advanced Data - Routing
 24. Fitter Messages
 25. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Fitter Summary                                                               ;
+-------------------------------+----------------------------------------------+
; Fitter Status                 ; Successful - Mon May 11 14:21:55 2009        ;
; Quartus II Version            ; 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition ;
; Revision Name                 ; chenggong                                    ;
; Top-level Entity Name         ; chenggong                                    ;
; Family                        ; Stratix II                                   ;
; Device                        ; EP2S15F484C3                                 ;
; Timing Models                 ; Final                                        ;
; Logic utilization             ; 0 %                                          ;
;     Combinational ALUTs       ; 0 / 12,480 ( 0 % )                           ;
;     Dedicated logic registers ; 0 / 12,480 ( 0 % )                           ;
; Total registers               ; 0                                            ;
; Total pins                    ; 8 / 343 ( 2 % )                              ;
; Total virtual pins            ; 0                                            ;
; Total block memory bits       ; 0 / 419,328 ( 0 % )                          ;
; DSP block 9-bit elements      ; 0 / 96 ( 0 % )                               ;
; Total PLLs                    ; 0 / 6 ( 0 % )                                ;
; Total DLLs                    ; 0 / 2 ( 0 % )                                ;
+-------------------------------+----------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP2S15F484C3                   ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;