chenggong.map.rpt

实现由一个4位十进制数码管（含小数点）显示结果

+-----------------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                          ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path          ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------+
; tcontrol.vhd                     ; yes             ; User VHDL File                     ; F:/quartus II/chenggong/tcontrol.vhd  ;
; cnt.vhd                          ; yes             ; User VHDL File                     ; F:/quartus II/chenggong/cnt.vhd       ;
; chenggong.bdf                    ; yes             ; User Block Diagram/Schematic File  ; F:/quartus II/chenggong/chenggong.bdf ;
; xianshi.vhd                      ; yes             ; Other                              ; F:/quartus II/chenggong/xianshi.vhd   ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+----------------------------------------------+-------+
; Resource                                     ; Usage ;
+----------------------------------------------+-------+
; Estimated ALUTs Used                         ; 0     ;
; Dedicated logic registers                    ; 0     ;
;                                              ;       ;
; Estimated ALUTs Unavailable                  ; 0     ;
;                                              ;       ;
; Total combinational functions                ; 0     ;
; Combinational ALUT usage by number of inputs ;       ;
;     -- 7 input functions                     ; 0     ;
;     -- 6 input functions                     ; 0     ;
;     -- 5 input functions                     ; 0     ;
;     -- 4 input functions                     ; 0     ;
;     -- <=3 input functions                   ; 0     ;
;                                              ;       ;
; Combinational ALUTs by mode                  ;       ;
;     -- normal mode                           ; 0     ;
;     -- extended LUT mode                     ; 0     ;
;     -- arithmetic mode                       ; 0     ;
;     -- shared arithmetic mode                ; 0     ;
;                                              ;       ;
; Estimated ALUT/register pairs used           ; 0     ;
;                                              ;       ;
; Total registers                              ; 0     ;
;     -- Dedicated logic registers             ; 0     ;
;     -- I/O registers                         ; 0     ;
;                                              ;       ;
;                                              ;       ;
; I/O pins                                     ; 8     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |chenggong                 ; 0 (0)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 8    ; 0            ; |chenggong          ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Web Edition
    Info: Processing started: Mon May 11 14:21:25 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chenggong -c chenggong
Info: Found 2 design units, including 1 entities, in source file tcontrol.vhd
    Info: Found design unit 1: tcontrol-behav
    Info: Found entity 1: tcontrol
Info: Found 2 design units, including 1 entities, in source file cnt.vhd
    Info: Found design unit 1: cnt-behav
    Info: Found entity 1: cnt
Info: Found 1 design units, including 1 entities, in source file chenggong.bdf
    Info: Found entity 1: chenggong
Info: Elaborating entity "chenggong" for the top level hierarchy
Warning: Pin "out3" is missing source
Warning: Pin "out2" is missing source
Warning: Pin "out1" is missing source
Warning: Pin "out0" is missing source
Info: Elaborating entity "cnt" for hierarchy "cnt:inst"
Warning: Using design file xianshi.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: xianshi-behav
    Info: Found entity 1: xianshi
Info: Elaborating entity "xianshi" for hierarchy "xianshi:inst8"
Warning (10036): Verilog HDL or VHDL warning at xianshi.vhd(17): object "C3" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at xianshi.vhd(18): object "F0" assigned a value but never read
Warning (10492): VHDL Process Statement warning at xianshi.vhd(23): signal "A" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(25): signal "in0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(26): signal "in1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(27): signal "in2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(28): signal "in3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(30): signal "in0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(31): signal "in1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(32): signal "in2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(33): signal "in3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(35): signal "in0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(36): signal "in1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(37): signal "in2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(38): signal "in3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(40): signal "in0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(41): signal "in1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(42): signal "in2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(43): signal "in3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(46): signal "A0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(47): signal "A1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(48): signal "A2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(49): signal "A3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xianshi.vhd(50): signal "C0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list