📄 hardware.lst
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//
// Ex: F_SACM_A2000_Initial:
// ...
// call F_SP_SACM_A2000_Init_ : S480/S240/MS01 is same
// ...
// retf
////////////////////////////////////////////////////////////////////////////////
F_SP_SACM_A2000_Init_:
0000BE43 40 92 R1=0x0000; // 24MHz, Fcpu=Fosc
0000BE44 19 D3 13 70 [P_SystemClock]=R1 // Frequency 20MHz
0000BE46 70 92 R1 = 0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000BE47 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
0000BE49 09 93 00 FD R1 = 0xfd00 // 16K
0000BE4B 19 D3 0A 70 [P_TimerA_Data] = R1
0000BE4D 09 93 A8 00 R1 = 0x00A8 // Set the DAC Ctrl
0000BE4F 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000BE51 09 93 FF FF R1 = 0xffff
0000BE53 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000BE55 40 92 R1 =0x0000 //
0000BE56 11 93 05 00 R1 = [R_InterruptStatus] //
0000BE58 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
0000BE5A 19 D3 05 00 [R_InterruptStatus] = R1 //
0000BE5C 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000BE5E 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
0000BE5F 40 92 R1 = 0x0000 // 24MHz Fosc
0000BE60 19 D3 13 70 [P_SystemClock]=R1 // Initial System Clock
0000BE62 70 92 R1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000BE63 19 D3 0B 70 [P_TimerA_Ctrl]=R1 // Initial Timer A
//R1 = 0xfd00 // 16K
0000BE65 09 93 ED FC R1 = 0xfced // 15.625K
0000BE67 19 D3 0A 70 [P_TimerA_Data]=R1
0000BE69 09 93 A8 00 R1 = 0x00A8 //
0000BE6B 19 D3 2A 70 [P_DAC_Ctrl] = R1 //
0000BE6D 09 93 FF FF R1 = 0xffff
0000BE6F 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000BE71 11 93 05 00 R1 = [R_InterruptStatus] //
0000BE73 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
0000BE75 19 D3 05 00 [R_InterruptStatus] = R1 //
0000BE77 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000BE79 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
0000BE7A 60 92 R1=0x0020;
0000BE7B 19 D3 13 70 [P_SystemClock]=R1
0000BE7D 09 93 A8 00 R1 = 0x00A8; //
0000BE7F 19 D3 2A 70 [P_DAC_Ctrl]= R1
0000BE81 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000BE82 19 D3 0B 70 [P_TimerA_Ctrl] = R1;
0000BE84 09 93 00 FE R1 = 0xfe00; // 24K
0000BE86 19 D3 0A 70 [P_TimerA_Data] = R1;
0000BE88 09 93 FF FF R1 = 0xffff
0000BE8A 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000BE8C 11 93 05 00 R1 = [R_InterruptStatus] //
0000BE8E 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
0000BE90 19 D3 05 00 [R_InterruptStatus] = R1 //
0000BE92 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000BE94 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
0000BE95 40 92 R1 = 0x0000; // 24MHz, Fcpu=Fosc
0000BE96 19 D3 13 70 [P_SystemClock] = R1; // Initial System Clock
0000BE98 70 92 R1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000BE99 19 D3 0B 70 [P_TimerA_Ctrl] = R1 // Initial Timer A
//R1 = 0x0003 // 8K
0000BE9B 40 92 R1 = 0x0000 // Fosc/2
0000BE9C 19 D3 0D 70 [P_TimerB_Ctrl] = R1; // Initial Timer B -> 8192
//R1 = 0xFFFF
0000BE9E 09 93 00 FA R1 = 0xFA00 // Any time for ADPCM channel 0,1
0000BEA0 19 D3 0C 70 [P_TimerB_Data] = R1 // 8K sample rate
0000BEA2 09 93 FF FF R1 = 0xffff
0000BEA4 19 D3 11 70 [P_INT_Clear] = R1 // Clear interrupt occuiped events
0000BEA6 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
0000BEA7 46 92 R1 = 0x0006
0000BEA8 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000BEAA 09 93 00 FE R1 = 0xFE00
0000BEAC 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000BEAE 11 93 05 00 R1 = [R_InterruptStatus] //
0000BEB0 09 A3 10 84 R1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
0000BEB2 19 D3 05 00 [R_InterruptStatus] = R1 //
0000BEB4 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000BEB6 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
0000BEB7 09 93 A8 00 R1 = 0x00A8
0000BEB9 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000BEBB 09 93 00 FE R1 = 0xFE00
0000BEBD 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000BEBF 11 93 05 00 R1 = [R_InterruptStatus] //
0000BEC1 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000BEC3 19 D3 05 00 [R_InterruptStatus] = R1 //
0000BEC5 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000BEC7 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
0000BEC8 09 93 A8 00 R1 = 0x00A8
0000BECA 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000BECC 09 93 9A FD R1 = 0xFD9A
0000BECE 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000BED0 11 93 05 00 R1 = [R_InterruptStatus] //
0000BED2 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000BED4 19 D3 05 00 [R_InterruptStatus] = R1 //
0000BED6 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000BED8 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
0000BED9 09 93 A8 00 R1 = 0x00A8
0000BEDB 19 D3 2A 70 [P_DAC_Ctrl] = R1
0000BEDD 09 93 00 FD R1 = 0xFD00
0000BEDF 19 D3 0A 70 [P_TimerA_Data] = R1 //
0000BEE1 11 93 05 00 R1 = [R_InterruptStatus] //
0000BEE3 09 A3 10 24 R1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
0000BEE5 19 D3 05 00 [R_InterruptStatus] = R1 //
0000BEE7 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000BEE9 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
0000BEEA 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
0000BEEB 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
0000BEED 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
0000BEEE 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
0000BEF0 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
0000BEF2 19 D3 0A 70 [P_TimerA_Data] = r1;
0000BEF4 75 92 r1 = 0x0035; // ADINI should be open (107)
0000BEF5 19 D3 15 70 [P_ADC_Ctrl] = r1;
0000BEF7 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
0000BEF9 19 D3 2A 70 [P_DAC_Ctrl] = r1;
0000BEFB 09 93 FF FF r1 = 0xffff;
0000BEFD 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
0000BEFF 11 93 05 00 R1 = [R_InterruptStatus] //
0000BF01 09 A3 00 20 R1 |= C_FIQ_TMA // Enable Timer A FIQ
0000BF03 19 D3 05 00 [R_InterruptStatus] = R1 //
0000BF05 19 D3 10 70 [P_INT_Ctrl] = R1 //
0000BF07 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
0000BF08 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
0000BF09 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
0000BF0B 09 93 00 FE R1=0xfe00; //24K @ 24.576MHz
0000BF0D 19 D3 0A 70 [P_TimerA_Data] = r1
0000BF0F 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
0000BF10 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
0000BF11 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
0000BF13 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
0000BF15 19 D3 0A 70 [P_TimerA_Data] = r1;
0000BF17 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
0000BF18 90 D4 push r1,r2 to [sp]
0000BF19 11 93 17 70 r1=[P_DAC1]
0000BF1B 09 B3 C0 FF r1 &= ~0x003f
0000BF1D 09 43 00 80 cmp r1,0x8000
0000BF1F 0E 0E jb L_RU_NormalUp
0000BF20 19 5E je L_RU_End
L_RU_DownLoop:
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