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📄 spi_master.lst

📁 DDS之AD9910驱动源码
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 00000010  2000      MOV         R0,#0x0
 00000012  1C04      MOV         R4,R0 ; ReceiveData
 00000014  ---- Variable 'ReceiveData' assigned to Register 'R4' ----
  106:     unsigned    char    i = 0;
 00000014  2300      MOV         R3,#0x0
 00000016  ---- Variable 'i' assigned to Register 'R3' ----
  107:     unsigned    int     iTemp = 0;
 00000016  9001      STR         R0,[R13,#0x4] ; iTemp
  110:     ControlValue = RegisterAddress;
 00000018  1C39      MOV         R1,R7 ; RegisterAddress
 0000001A  A800      ADD         R0,R13,#0x0
 0000001C  7001      STRB        R1,[R0,#0x0] ; ControlValue
  112:     CLR_SCL();
 0000001E  4800      LDR         R0,=0xFFFFF430
 00000020  6801      LDR         R1,[R0,#0x0]
 00000022  4800      LDR         R0,=0x40000
 00000024  4381      BIC         R1,R0
 00000026  4800      LDR         R0,=0xFFFFF430
 00000028  6001      STR         R1,[R0,#0x0]
  113:     delay(1);   
 0000002A  2001      MOV         R0,#0x1
 0000002C  F7FF      BL          delay?T  ; T=0x0001  (1)
 0000002E  FFE8      BL          delay?T  ; T=0x0001  (2)
  114:     SET_CS();
 00000030  4800      LDR         R0,=0xFFFFF460
 00000032  6801      LDR         R1,[R0,#0x0]
 00000034  4800      LDR         R0,=0x20000
 00000036  4301      ORR         R1,R0
 00000038  4800      LDR         R0,=0xFFFFF460
 0000003A  6001      STR         R1,[R0,#0x0]
ARM COMPILER V2.53,  SPI_Master                                                            25/11/08  15:54:12  PAGE 9   

  115:     delay(1);
 0000003C  2001      MOV         R0,#0x1
 0000003E  F7FF      BL          delay?T  ; T=0x0001  (1)
 00000040  FFDF      BL          delay?T  ; T=0x0001  (2)
  116:     CLR_CS();    //bring CS low
 00000042  4800      LDR         R0,=0xFFFFF460
 00000044  6801      LDR         R1,[R0,#0x0]
 00000046  4800      LDR         R0,=0x20000
 00000048  4381      BIC         R1,R0
 0000004A  4800      LDR         R0,=0xFFFFF460
 0000004C  6001      STR         R1,[R0,#0x0]
  117:     delay(1);
 0000004E  2001      MOV         R0,#0x1
 00000050  F7FF      BL          delay?T  ; T=0x0001  (1)
 00000052  FFD6      BL          delay?T  ; T=0x0001  (2)
  120:     for(i=0; i<8; i++)
 00000054  2300      MOV         R3,#0x0
 00000056  E02A      B           L_26  ; T=0x000000AE
 00000058          L_27:
  122:         CLR_SCL();
 00000058  4800      LDR         R0,=0xFFFFF430
 0000005A  6801      LDR         R1,[R0,#0x0]
 0000005C  4800      LDR         R0,=0x40000
 0000005E  4381      BIC         R1,R0
 00000060  4800      LDR         R0,=0xFFFFF430
 00000062  6001      STR         R1,[R0,#0x0]
  123:         if(0x80 == (ControlValue & 0x80))
 00000064  A800      ADD         R0,R13,#0x0
 00000066  7800      LDRB        R0,[R0,#0x0] ; ControlValue
 00000068  2180      MOV         R1,#0x80
 0000006A  4208      TST         R0,R1
 0000006C  D006      BEQ         L_29  ; T=0x0000007C
  125:             SET_SDIO();   //Send one to SDIO pin
 0000006E  4800      LDR         R0,=0xFFFFF430
 00000070  6801      LDR         R1,[R0,#0x0]
 00000072  4800      LDR         R0,=0x80000
 00000074  4301      ORR         R1,R0
 00000076  4800      LDR         R0,=0xFFFFF430
 00000078  6001      STR         R1,[R0,#0x0]
  126:         }
 0000007A  E005      B           L_30  ; T=0x00000088
 0000007C          L_29:
  129:             CLR_SDIO();   //Send zero to SDIO pin
 0000007C  4800      LDR         R0,=0xFFFFF430
 0000007E  6801      LDR         R1,[R0,#0x0]
 00000080  4800      LDR         R0,=0x80000
 00000082  4381      BIC         R1,R0
 00000084  4800      LDR         R0,=0xFFFFF430
 00000086  6001      STR         R1,[R0,#0x0]
  130:         }
 00000088          L_30:
  131:         delay(1);
 00000088  2001      MOV         R0,#0x1
 0000008A  F7FF      BL          delay?T  ; T=0x0001  (1)
 0000008C  FFB9      BL          delay?T  ; T=0x0001  (2)
  132:         SET_SCL();
 0000008E  4800      LDR         R0,=0xFFFFF430
 00000090  6801      LDR         R1,[R0,#0x0]
 00000092  4800      LDR         R0,=0x40000
 00000094  4301      ORR         R1,R0
 00000096  4800      LDR         R0,=0xFFFFF430
 00000098  6001      STR         R1,[R0,#0x0]
  133:         delay(1);
 0000009A  2001      MOV         R0,#0x1
 0000009C  F7FF      BL          delay?T  ; T=0x0001  (1)
 0000009E  FFB0      BL          delay?T  ; T=0x0001  (2)
ARM COMPILER V2.53,  SPI_Master                                                            25/11/08  15:54:12  PAGE 10  

  134:         ControlValue <<= 1; //Rotate data
 000000A0  A800      ADD         R0,R13,#0x0
 000000A2  7801      LDRB        R1,[R0,#0x0] ; ControlValue
 000000A4  0049      LSL         R1,R1,#0x1
 000000A6  7001      STRB        R1,[R0,#0x0] ; ControlValue
  135:     }
 000000A8  3301      ADD         R3,#0x1
 000000AA  061B      LSL         R3,R3,#0x18
 000000AC  0E1B      LSR         R3,R3,#0x18
 000000AE          L_26:
 000000AE  1C18      MOV         R0,R3 ; i
 000000B0  0600      LSL         R0,R0,#0x18 ; i
 000000B2  0E00      LSR         R0,R0,#0x18
 000000B4  2808      CMP         R0,#0x8
 000000B6  DBCF      BLT         L_27  ; T=0x00000058
  136:     CLR_SCL();
 000000B8  4800      LDR         R0,=0xFFFFF430
 000000BA  6801      LDR         R1,[R0,#0x0]
 000000BC  4800      LDR         R0,=0x40000
 000000BE  4381      BIC         R1,R0
 000000C0  4800      LDR         R0,=0xFFFFF430
 000000C2  6001      STR         R1,[R0,#0x0]
  137:     delay(2);
 000000C4  2002      MOV         R0,#0x2
 000000C6  F7FF      BL          delay?T  ; T=0x0001  (1)
 000000C8  FF9B      BL          delay?T  ; T=0x0001  (2)
  140:     for (RegisterIndex=NumberofRegisters; RegisterIndex>0; RegisterIndex--)
 000000CA  1C35      MOV         R5,R6 ; NumberofRegisters
 000000CC  062D      LSL         R5,R5,#0x18 ; NumberofRegisters
 000000CE  0E2D      LSR         R5,R5,#0x18
 000000D0  E031      B           L_33  ; T=0x00000136
  142:         for(i=0; i<32; i++)
 000000D2          L_40:
 000000D2  2300      MOV         R3,#0x0
 000000D4  E01E      B           L_38  ; T=0x00000114
 000000D6          L_39:
  144:             CLR_SCL();
 000000D6  4800      LDR         R0,=0xFFFFF430
 000000D8  6801      LDR         R1,[R0,#0x0]
 000000DA  4800      LDR         R0,=0x40000
 000000DC  4381      BIC         R1,R0
 000000DE  4800      LDR         R0,=0xFFFFF430
 000000E0  6001      STR         R1,[R0,#0x0]
  145:             delay(1);
 000000E2  2001      MOV         R0,#0x1
 000000E4  F7FF      BL          delay?T  ; T=0x0001  (1)
 000000E6  FF8C      BL          delay?T  ; T=0x0001  (2)
  146:             SET_SCL();
 000000E8  4800      LDR         R0,=0xFFFFF430
 000000EA  6801      LDR         R1,[R0,#0x0]
 000000EC  4800      LDR         R0,=0x40000
 000000EE  4301      ORR         R1,R0
 000000F0  4800      LDR         R0,=0xFFFFF430
 000000F2  6001      STR         R1,[R0,#0x0]
  147:             ReceiveData <<= 1;      //Rotate data
 000000F4  0064      LSL         R4,R4,#0x1 ; ReceiveData
  148:             iTemp = GP4DAT;         //Read SDO of AD9910
 000000F6  4800      LDR         R0,=0xFFFFF460
 000000F8  6800      LDR         R0,[R0,#0x0]
 000000FA  9001      STR         R0,[R13,#0x4] ; iTemp
  149:             if(0x00000010 == (iTemp & 0x00000010))
 000000FC  9801      LDR         R0,[R13,#0x4] ; iTemp
 000000FE  2110      MOV         R1,#0x10
 00000100  4208      TST         R0,R1
 00000102  D001      BEQ         L_41  ; T=0x00000108
  151:                 ReceiveData |= 1;   
ARM COMPILER V2.53,  SPI_Master                                                            25/11/08  15:54:12  PAGE 11  

 00000104  2001      MOV         R0,#0x1
 00000106  4304      ORR         R4,R0
  152:             }
 00000108          L_41:
  153:             delay(1);
 00000108  2001      MOV         R0,#0x1
 0000010A  F7FF      BL          delay?T  ; T=0x0001  (1)
 0000010C  FF79      BL          delay?T  ; T=0x0001  (2)
  154:         }
 0000010E  3301      ADD         R3,#0x1
 00000110  061B      LSL         R3,R3,#0x18
 00000112  0E1B      LSR         R3,R3,#0x18
 00000114          L_38:
 00000114  1C18      MOV         R0,R3 ; i
 00000116  0600      LSL         R0,R0,#0x18 ; i
 00000118  0E00      LSR         R0,R0,#0x18
 0000011A  2820      CMP         R0,#0x20
 0000011C  DBDB      BLT         L_39  ; T=0x000000D6
  155:         *(RegisterData + RegisterIndex - 1) = ReceiveData;
 0000011E  1C21      MOV         R1,R4 ; ReceiveData
 00000120  1C28      MOV         R0,R5 ; RegisterIndex
 00000122  0606      LSL         R6,R0,#0x18 ; RegisterIndex
 00000124  1636      ASR         R6,R6,#0x18
 00000126  00B6      LSL         R6,R6,#0x2
 00000128  1C10      MOV         R0,R2 ; RegisterData
 0000012A  1980      ADD         R0,R6 ; RegisterData
 0000012C  3804      SUB         R0,#0x4
 0000012E  6001      STR         R1,[R0,#0x0]
  156:     }
 00000130  3D01      SUB         R5,#0x1
 00000132  062D      LSL         R5,R5,#0x18
 00000134  162D      ASR         R5,R5,#0x18
 00000136          L_33:
 00000136  1C28      MOV         R0,R5 ; RegisterIndex
 00000138  0600      LSL         R0,R0,#0x18 ; RegisterIndex
 0000013A  1600      ASR         R0,R0,#0x18
 0000013C  2800      CMP         R0,#0x0
 0000013E  DCC8      BGT         L_40  ; T=0x000000D2
  157:     CLR_SCL();
 00000140  4800      LDR         R0,=0xFFFFF430
 00000142  6801      LDR         R1,[R0,#0x0]
 00000144  4800      LDR         R0,=0x40000
 00000146  4381      BIC         R1,R0
 00000148  4800      LDR         R0,=0xFFFFF430
 0000014A  6001      STR         R1,[R0,#0x0]
  158:     delay(1);
 0000014C  2001      MOV         R0,#0x1
 0000014E  F7FF      BL          delay?T  ; T=0x0001  (1)
 00000150  FF57      BL          delay?T  ; T=0x0001  (2)
  159:     SET_CS();   //bring CS high again
 00000152  4800      LDR         R0,=0xFFFFF460
 00000154  6801      LDR         R1,[R0,#0x0]
 00000156  4800      LDR         R0,=0x20000
 00000158  4301      ORR         R1,R0
 0000015A  4800      LDR         R0,=0xFFFFF460
 0000015C  6001      STR         R1,[R0,#0x0]
 0000015E            ; SCOPE-END
  160: } 
 0000015E  B002      ADD         R13,#0x8
 00000160  BCF0      POP         {R4-R7}
 00000162  BC08      POP         {R3}
 00000164  4718      BX          R3
 00000166          ENDP ; 'ReadFromAD9910ViaSpi?T'



Module Information          Static
----------------------------------
ARM COMPILER V2.53,  SPI_Master                                                            25/11/08  15:54:12  PAGE 12  

  code size            =    ------
  data size            =    ------
  const size           =    ------
End of Module Information.


ARM COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)

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