📄 spi_master.lst
字号:
00000028 F7FF BL delay?T ; T=0x0001 (1)
0000002A FFEA BL delay?T ; T=0x0001 (2)
43: SET_CS();
ARM COMPILER V2.53, SPI_Master 25/11/08 15:54:12 PAGE 5
0000002C 4800 LDR R0,=0xFFFFF460
0000002E 6801 LDR R1,[R0,#0x0]
00000030 4800 LDR R0,=0x20000
00000032 4301 ORR R1,R0
00000034 4800 LDR R0,=0xFFFFF460
00000036 6001 STR R1,[R0,#0x0]
44: delay(1);
00000038 2001 MOV R0,#0x1
0000003A F7FF BL delay?T ; T=0x0001 (1)
0000003C FFE1 BL delay?T ; T=0x0001 (2)
45: CLR_CS(); //bring CS low
0000003E 4800 LDR R0,=0xFFFFF460
00000040 6801 LDR R1,[R0,#0x0]
00000042 4800 LDR R0,=0x20000
00000044 4381 BIC R1,R0
00000046 4800 LDR R0,=0xFFFFF460
00000048 6001 STR R1,[R0,#0x0]
46: delay(1);
0000004A 2001 MOV R0,#0x1
0000004C F7FF BL delay?T ; T=0x0001 (1)
0000004E FFD8 BL delay?T ; T=0x0001 (2)
49: for(i=0; i<8; i++)
00000050 2300 MOV R3,#0x0
00000052 E02A B L_7 ; T=0x000000AA
00000054 L_8:
51: CLR_SCL();
00000054 4800 LDR R0,=0xFFFFF430
00000056 6801 LDR R1,[R0,#0x0]
00000058 4800 LDR R0,=0x40000
0000005A 4381 BIC R1,R0
0000005C 4800 LDR R0,=0xFFFFF430
0000005E 6001 STR R1,[R0,#0x0]
52: if(0x80 == (ControlValue & 0x80))
00000060 A800 ADD R0,R13,#0x0
00000062 7800 LDRB R0,[R0,#0x0] ; ControlValue
00000064 2180 MOV R1,#0x80
00000066 4208 TST R0,R1
00000068 D006 BEQ L_10 ; T=0x00000078
54: SET_SDIO(); //Send one to SDIO pin
0000006A 4800 LDR R0,=0xFFFFF430
0000006C 6801 LDR R1,[R0,#0x0]
0000006E 4800 LDR R0,=0x80000
00000070 4301 ORR R1,R0
00000072 4800 LDR R0,=0xFFFFF430
00000074 6001 STR R1,[R0,#0x0]
55: }
00000076 E005 B L_11 ; T=0x00000084
00000078 L_10:
58: CLR_SDIO(); //Send zero to SDIO pin
00000078 4800 LDR R0,=0xFFFFF430
0000007A 6801 LDR R1,[R0,#0x0]
0000007C 4800 LDR R0,=0x80000
0000007E 4381 BIC R1,R0
00000080 4800 LDR R0,=0xFFFFF430
00000082 6001 STR R1,[R0,#0x0]
59: }
00000084 L_11:
60: delay(1);
00000084 2001 MOV R0,#0x1
00000086 F7FF BL delay?T ; T=0x0001 (1)
00000088 FFBB BL delay?T ; T=0x0001 (2)
61: SET_SCL();
0000008A 4800 LDR R0,=0xFFFFF430
0000008C 6801 LDR R1,[R0,#0x0]
0000008E 4800 LDR R0,=0x40000
00000090 4301 ORR R1,R0
ARM COMPILER V2.53, SPI_Master 25/11/08 15:54:12 PAGE 6
00000092 4800 LDR R0,=0xFFFFF430
00000094 6001 STR R1,[R0,#0x0]
62: delay(1);
00000096 2001 MOV R0,#0x1
00000098 F7FF BL delay?T ; T=0x0001 (1)
0000009A FFB2 BL delay?T ; T=0x0001 (2)
63: ControlValue <<= 1; //Rotate data
0000009C A800 ADD R0,R13,#0x0
0000009E 7801 LDRB R1,[R0,#0x0] ; ControlValue
000000A0 0049 LSL R1,R1,#0x1
000000A2 7001 STRB R1,[R0,#0x0] ; ControlValue
64: }
000000A4 3301 ADD R3,#0x1
000000A6 061B LSL R3,R3,#0x18
000000A8 0E1B LSR R3,R3,#0x18
000000AA L_7:
000000AA 1C18 MOV R0,R3 ; i
000000AC 0600 LSL R0,R0,#0x18 ; i
000000AE 0E00 LSR R0,R0,#0x18
000000B0 2808 CMP R0,#0x8
000000B2 DBCF BLT L_8 ; T=0x00000054
65: CLR_SCL();
000000B4 4800 LDR R0,=0xFFFFF430
000000B6 6801 LDR R1,[R0,#0x0]
000000B8 4800 LDR R0,=0x40000
000000BA 4381 BIC R1,R0
000000BC 4800 LDR R0,=0xFFFFF430
000000BE 6001 STR R1,[R0,#0x0]
66: delay(2);
000000C0 2002 MOV R0,#0x2
000000C2 F7FF BL delay?T ; T=0x0001 (1)
000000C4 FF9D BL delay?T ; T=0x0001 (2)
69: for (RegisterIndex=NumberofRegisters; RegisterIndex>0; RegisterIndex--)
000000C6 1C34 MOV R4,R6 ; NumberofRegisters
000000C8 0624 LSL R4,R4,#0x18 ; NumberofRegisters
000000CA 0E24 LSR R4,R4,#0x18
000000CC E039 B L_14 ; T=0x00000142
000000CE L_15:
71: ValueToWrite = *(RegisterData + RegisterIndex - 1);
000000CE 1C20 MOV R0,R4 ; RegisterIndex
000000D0 0601 LSL R1,R0,#0x18 ; RegisterIndex
000000D2 1609 ASR R1,R1,#0x18
000000D4 0089 LSL R1,R1,#0x2
000000D6 1C10 MOV R0,R2 ; RegisterData
000000D8 1840 ADD R0,R1 ; RegisterData
000000DA 3804 SUB R0,#0x4
000000DC 6805 LDR R5,[R0,#0x0]
72: for (i=0; i<32; i++)
000000DE 2300 MOV R3,#0x0
000000E0 E027 B L_19 ; T=0x00000132
000000E2 L_20:
74: CLR_SCL();
000000E2 4800 LDR R0,=0xFFFFF430
000000E4 6801 LDR R1,[R0,#0x0]
000000E6 4800 LDR R0,=0x40000
000000E8 4381 BIC R1,R0
000000EA 4800 LDR R0,=0xFFFFF430
000000EC 6001 STR R1,[R0,#0x0]
75: if(0x80000000 == (ValueToWrite & 0x80000000))
000000EE 1C28 MOV R0,R5 ; ValueToWrite
000000F0 4800 LDR R1,=0x80000000
000000F2 4008 AND R0,R1
000000F4 42C8 CMN R0,R1
000000F6 D106 BNE L_22 ; T=0x00000106
77: SET_SDIO(); //Send one to SDIO pin
000000F8 4800 LDR R0,=0xFFFFF430
ARM COMPILER V2.53, SPI_Master 25/11/08 15:54:12 PAGE 7
000000FA 6801 LDR R1,[R0,#0x0]
000000FC 4800 LDR R0,=0x80000
000000FE 4301 ORR R1,R0
00000100 4800 LDR R0,=0xFFFFF430
00000102 6001 STR R1,[R0,#0x0]
78: }
00000104 E005 B L_23 ; T=0x00000112
00000106 L_22:
81: CLR_SDIO(); //Send zero to SDIO pin
00000106 4800 LDR R0,=0xFFFFF430
00000108 6801 LDR R1,[R0,#0x0]
0000010A 4800 LDR R0,=0x80000
0000010C 4381 BIC R1,R0
0000010E 4800 LDR R0,=0xFFFFF430
00000110 6001 STR R1,[R0,#0x0]
82: }
00000112 L_23:
83: delay(1);
00000112 2001 MOV R0,#0x1
00000114 F7FF BL delay?T ; T=0x0001 (1)
00000116 FF74 BL delay?T ; T=0x0001 (2)
84: SET_SCL();
00000118 4800 LDR R0,=0xFFFFF430
0000011A 6801 LDR R1,[R0,#0x0]
0000011C 4800 LDR R0,=0x40000
0000011E 4301 ORR R1,R0
00000120 4800 LDR R0,=0xFFFFF430
00000122 6001 STR R1,[R0,#0x0]
85: delay(1);
00000124 2001 MOV R0,#0x1
00000126 F7FF BL delay?T ; T=0x0001 (1)
00000128 FF6B BL delay?T ; T=0x0001 (2)
86: ValueToWrite <<= 1; //Rotate data
0000012A 006D LSL R5,R5,#0x1 ; ValueToWrite
87: }
0000012C 3301 ADD R3,#0x1
0000012E 061B LSL R3,R3,#0x18
00000130 0E1B LSR R3,R3,#0x18
00000132 L_19:
00000132 1C18 MOV R0,R3 ; i
00000134 0600 LSL R0,R0,#0x18 ; i
00000136 0E00 LSR R0,R0,#0x18
00000138 2820 CMP R0,#0x20
0000013A DBD2 BLT L_20 ; T=0x000000E2
88: }
0000013C 3C01 SUB R4,#0x1
0000013E 0624 LSL R4,R4,#0x18
00000140 1624 ASR R4,R4,#0x18
00000142 L_14:
00000142 1C20 MOV R0,R4 ; RegisterIndex
00000144 0600 LSL R0,R0,#0x18 ; RegisterIndex
00000146 1600 ASR R0,R0,#0x18
00000148 2800 CMP R0,#0x0
0000014A DCC0 BGT L_15 ; T=0x000000CE
89: CLR_SCL();
0000014C 4800 LDR R0,=0xFFFFF430
0000014E 6801 LDR R1,[R0,#0x0]
00000150 4800 LDR R0,=0x40000
00000152 4381 BIC R1,R0
00000154 4800 LDR R0,=0xFFFFF430
00000156 6001 STR R1,[R0,#0x0]
90: delay(1);
00000158 2001 MOV R0,#0x1
0000015A F7FF BL delay?T ; T=0x0001 (1)
0000015C FF51 BL delay?T ; T=0x0001 (2)
91: SET_CS(); //bring CS high again
ARM COMPILER V2.53, SPI_Master 25/11/08 15:54:12 PAGE 8
0000015E 4800 LDR R0,=0xFFFFF460
00000160 6801 LDR R1,[R0,#0x0]
00000162 4800 LDR R0,=0x20000
00000164 4301 ORR R1,R0
00000166 4800 LDR R0,=0xFFFFF460
00000168 6001 STR R1,[R0,#0x0]
92: IO_Update();
0000016A F7FF BL IO_Update?T ; T=0x0001 (1)
0000016C FF49 BL IO_Update?T ; T=0x0001 (2)
0000016E ; SCOPE-END
93: }
0000016E B001 ADD R13,#0x4
00000170 BCF0 POP {R4-R7}
00000172 BC08 POP {R3}
00000174 4718 BX R3
00000176 ENDP ; 'WriteToAD9910ViaSpi?T'
*** CODE SEGMENT '?PR?ReadFromAD9910ViaSpi?T?SPI_Master':
101: void ReadFromAD9910ViaSpi(unsigned char RegisterAddress, unsigned char NumberofRegisters, unsigned int *RegisterD
-ata)
00000000 B5F0 PUSH {R4-R7,LR}
00000002 ---- Variable 'RegisterData' assigned to Register 'R2' ----
00000002 1C0E MOV R6,R1 ; NumberofRegisters
00000004 ---- Variable 'NumberofRegisters' assigned to Register 'R6' ----
00000004 1C07 MOV R7,R0 ; RegisterAddress
00000006 ---- Variable 'RegisterAddress' assigned to Register 'R7' ----
00000006 B082 SUB R13,#0x8
102: {
00000008 ; SCOPE-START
103: unsigned char ControlValue = 0;
00000008 2100 MOV R1,#0x0
0000000A A800 ADD R0,R13,#0x0
0000000C 7001 STRB R1,[R0,#0x0] ; ControlValue
104: signed char RegisterIndex = 0;
0000000E 2500 MOV R5,#0x0
00000010 ---- Variable 'RegisterIndex' assigned to Register 'R5' ----
105: unsigned int ReceiveData = 0;
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