ex1.spj

来自「verilog source code nand gate」· SPJ 代码 · 共 27 行

[Files]
0=ex1.v


[Settings]
Mode=Debug
Version=97.1
[Position]
Width=768
Height=530
X=110
Y=145
[Group0]
Name=Default
0=stimulus:OUT_OR
1=stimulus:OUT_NOT
2=stimulus:OUT_AND
3=stimulus:IN2
4=stimulus:IN1
[WindowPos]
OpenWindows=
Output=0,1,0,-1,0,-1,0,0,668,253
[Options]
DebugEnable=Yes
CCEnable=No
CcOpEnable=No