phasemod.v

来自「比较先进的直接数字频率合成器的设计。可用于频率的合成。」· Verilog 代码 · 共 61 行

/*******************************************************************************
****************************************************************************
 **                                                                             
 **                                                                             
 ** Project Name         : DDS                                            
 **                                                                             
 ** Author               : Daniel J. Morelli
 ** Creation Date        : 03/03/96 22:27:56                                              
 ** Version Number       : 1.0                                                 
 **                                                                             
 ** Revision History     :                                                      
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 ** Date          Initials         Modification                                 
 **                                                                             
 **                                                                             
 ** Description          :                                                      
 **                                                                             
 ** This module will take the phase value from the phase accumulator and
 ** modulate it with the synchronous version of the modulation phase word.
 ** 
 **                                                                             
 *******************************************************************************/

 module phasemod (
	SYSCLK,			// system clock input
	RESETN,			// global reset
	SYNCPHSWD,		// synchronous phase word
	PHASE,			// 8 bit quantized phase value
	MCOS,				// modulated digital cos output
	MSIN,				// modulated digital sin output
	MODPHASE);		// modulated phase output

// Port types

input SYSCLK, RESETN;
input[7:0] SYNCPHSWD, PHASE;

output MCOS, MSIN;
output[7:0] MODPHASE;

wire[7:0] mphs;				// modulated phase from adder
reg[7:0] mphsreg;			// modulated phase registered
wire c;					// carry from adder not used

supply0 gnd;									// low input

// design architecture
	assign MODPHASE = mphsreg;
	assign MSIN = ~mphsreg[7];
	assign MCOS = ~(mphsreg[7] ^ mphsreg[6]);

  	claadd8s U_add(PHASE, SYNCPHSWD, gnd, mphs, c);
 
	always @(posedge SYSCLK or negedge RESETN)
		if (!RESETN)
			mphsreg <= 8'h00;
		else
			mphsreg <= mphs;

endmodule