rtl.src

spi slave 8bit address 1bit r/w 7bit number data

+access+rwc
+notimingcheck
+no_tchk_msg
+no_specify
+librescan
+libext+.v+.vp+.mdlp+.vc+.vh+.vm+.sv
+define+functional
+loadpli1=debpli:deb_PLIPtr
+ncnontcglitch
+bus_conflict_off 
//+mixedlang 
//+define+FULLCHIP 


//----------------------------------------------------------------------------
// User
//----------------------------------------------------------------------------
        +incdir+.+../rtl

        +incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/packages/gtech/src_ver
        +incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw01/src_ver
        +incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw02/src_ver
        +incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw06/src_ver
/*
	+incdir+../../../../library/xilinx_8.1/verilog
	+incdir+../../../../library/xilinx_8.1/verilog/XilinxCoreLib
	+incdir+../../../../library/xilinx_8.1/verilog/simprims
	+incdir+../../../../library/xilinx_8.1/verilog/unisims
*/
// Models

// Source
        -y ../rtl

// Test Bench File
       ./testblock_tb.v
 
        
//----------------------------------------------------------------------------
// Library
//----------------------------------------------------------------------------

// Models

//	-v /home302/princess/TG901/LIB/IC/sc-x/verilog/csm18ic.v
//	-v /home302/princess/TG901/LIB/IC/IO/io-il/verilog/iogp_il_csm18ic_verilog.v

// SMIC 0.18um Library
//	-v /proj/techlib/smic/018um/release/2005q4v1/vlog/smic18.v 
//	-v /proj/techlib/smic/018um/release/2005q4v1/vlog/SP018W_V1p7.v 
//	-v /proj/techlib/smic/018um/release/2005q4v1/S018PLLGS_500_EDK_V_1_4_4/vlog/S018PLLGS_500.v 
//	-v /proj/techlib/smic/018um/release/2005q4v1/smic18_ICG/v1.1/vlog/smic18_GC.v 
//	-y /proj/techlib/smic/018um/release/2005q4v1/mem/vlog