spi_core.log

spi slave 8bit address 1bit r/w 7bit number data

ncverilog: 05.30-s007: (c) Copyright 1995-2004 Cadence Design Systems, Inc.
TOOL:	ncverilog	05.30-s007: Started on Mar 06, 2009 at 15:06:14
ncverilog
	testblock_tb.v
	-f rtl.src
		+access+rwc
		+notimingcheck
		+no_tchk_msg
		+no_specify
		+librescan
		+libext+.v+.vp+.mdlp+.vc+.vh+.vm+.sv
		+define+functional
		+loadpli1=debpli:deb_PLIPtr
		+ncnontcglitch
		+bus_conflict_off
		+incdir+.+../rtl
		+incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/packages/gtech/src_ver
		+incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw01/src_ver
		+incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw02/src_ver
		+incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw06/src_ver
		-y
		../rtl
		./testblock_tb.v
	-l
	spi_core.log
Loading snapshot worklib.testblock_tb:v .................... Done
SYSTEM ERROR:   VPI       LOADFL
         Failed to load dynamic library debpli
  ld.so.1: ncsim: fatal: debpli.so: open failed: No such file or directory
ncsim> source /home_wing/tools/cadence/Incisive/tools/inca/files/ncsimrc
ncsim> run

Warning!  $shm_open already done
            File: ./testblock_tb.v, line = 1174, pos = 17
           Scope: testblock_tb
            Time: 0 FS + 0

ncsim: *W,VFOPTW: File ./READ_DATA.dat being opened by Initial stmt (file: ./testblock_tb.v, line: 1117 in worklib.testblock_tb [module]) has been opened earlier.
Simulation complete via $finish(1) at time 63 US + 0
./testblock_tb.v:1167 		$finish;
ncsim> exit
TOOL:	ncverilog	05.30-s007: Exiting on Mar 06, 2009 at 15:06:18  (total: 00:00:04)