testblock.v

spi slave 8bit address 1bit r/w 7bit number data

//-----------------------------------------------------------------------------
//
// Title       : No Title
// Design      : spi
// Author      : 猎?鹊
// Company     : TG
//
//-----------------------------------------------------------------------------
//
// File        : c:\My_Designs\spi_final\spi\compile\test_block.v
// Generated   : Wed Feb 25 11:13:33 2009
// From        : c:/My_Designs/spi_final/spi/src/test_block.bde
// By          : Bde2Verilog ver. 2.01
//
//-----------------------------------------------------------------------------
//
// Description : 
//


module testblock (i_nreset,i_sclk,i_spi_clk,i_spi_cse,i_spi_en,i_spi_sdi,o_spi_sdo,o_busy,o_error,o_done) ;

// ------------ Port declarations --------- //
input i_nreset;
wire i_nreset;
input i_sclk;
wire i_sclk;
input i_spi_clk;
wire i_spi_clk;
input i_spi_cse;
wire i_spi_cse;
input i_spi_en;
wire i_spi_en;
input i_spi_sdi;
wire i_spi_sdi;
output o_spi_sdo;
wire o_spi_sdo;	   
output o_busy;
wire o_busy;
output o_done;
wire o_done;
output o_error;
wire o_error;


// ----------- Signal declarations -------- //
wire w_rdat_rx_wen;
wire w_tdat_tx_req;
wire [7:0] w_addr;
wire [7:0] w_rdat_rx;
wire [7:0] w_tdat_tx_rdat;
wire w_out_valid;


// -------- Component instantiations -------//

spi_core_slave u_spi_core_slave
(
	.i_nreset(i_nreset),
	.i_sclk(i_sclk),
	.i_spi_clk(i_spi_clk),
	.i_spi_cse(i_spi_cse),
	.i_spi_en(i_spi_en),
	.i_spi_sdi(i_spi_sdi),	 
	.i_tdat_input_en(w_out_valid),
	.i_tdat_tx_rdat(w_tdat_tx_rdat),
	.o_addr(w_addr),
	.o_rdat_rx(w_rdat_rx),
	.o_rdat_rx_wen(w_rdat_rx_wen),
	.o_spi_sdo(o_spi_sdo),
	.o_tdat_tx_req(w_tdat_tx_req) ,	  
	
	.o_error (o_error),
	.o_busy (o_busy),
	.o_done (o_done)
);
  
mem_8_64 mem(
	.addr(w_addr[7:0]),
	.clk(i_sclk),
	.din(w_rdat_rx[7:0]),
	.dout(w_tdat_tx_rdat[7:0]),
	.en(w_tdat_tx_req),
	.we(w_rdat_rx_wen)
);



always @(posedge i_sclk or negedge i_nreset) begin
	if(!i_nreset) 		w_out_valid  <=  1'b0;
	else 
     	w_out_valid<=w_tdat_tx_req;
end


endmodule