spi_core_slave.v

spi slave 8bit address 1bit r/w 7bit number data

						    	   N_ST <= NUMBER;
	    			    else 	   N_ST <= ADDR;			   		
		  NUMBER :	if(r_bit_cnt  == p_number_wth )
				               if(TX_RX_NST_info)   N_ST <= RXDATA;     // 0: Transfer(READ) 1: receive data(WRITE)
				               else  N_ST <= TXDATA;				  
			               else  N_ST <= NUMBER;  				   				
		 TXDATA : 		if( (r_bit_cnt == p_dat_wth ) & (r_sl_word_no == r_number_rx ) ) 	
			                     	N_ST <= DONE;
				            else    	N_ST <= TXDATA;								
	  	 RXDATA : 		if( (r_bit_cnt == p_dat_wth ) & (r_sl_word_no == r_number_rx) )				
						            N_ST <= DONE;							
			    	       else	   N_ST <= RXDATA;
		 DONE :    if  (i_spi_cse==  p_cse_pol)
			             N_ST <= IDLE;  
		                else 				  
					     N_ST <=DONE;  
//----------------------------------------		 
		default :	N_ST <= IDLE;
	
	endcase
end										


	   
 
//-----------------------------------------
// ### Slave status signal generation ###
//-----------------------------------------
always @(posedge i_sclk or negedge i_nreset) begin
	if(!i_nreset) begin 
					r_rdat_rx_done <= 1'b0;
					r_addr_rx_done <= 1'b0;	
					r_number_rx_done <= 1'b0;	
	end
	else begin
		case (C_ST) 		                                           
											
			ADDR :	if( (r_bit_cnt == p_addr_wth))									 // ADDRESS data  is completed to tranfer
                        if(w_cap_en)        r_addr_rx_done <= 1'b1;
                        else if(w_chg_en)   r_addr_rx_done <= 1'b0;
                        else                r_addr_rx_done <= r_addr_rx_done;	  
                    else                    r_addr_rx_done <= 1'b0;	
						
			NUMBER :	if( (r_bit_cnt == p_number_wth))							   // NUMBER data  is completed to tranfer
                        if(w_cap_en)        r_number_rx_done <= 1'b1;
                        else if(w_chg_en)   r_number_rx_done <= 1'b0;
                        else                r_number_rx_done <= r_number_rx_done;
                        else                r_number_rx_done <= 1'b0;	
									
						
    		 RXDATA :	if(r_bit_cnt == p_dat_wth) 								      	 // one RXDATA Burst  data is completed to receive
                        if(w_cap_en)        r_rdat_rx_done <= 1'b1;
                        else if(w_chg_en)   r_rdat_rx_done <= 1'b0;
                        else                r_rdat_rx_done <= r_rdat_rx_done;
                        else                    r_rdat_rx_done <= 1'b0;
				
									 
			default : begin	r_rdat_rx_done <= 1'b0;
				                    r_addr_rx_done <= 1'b0;	  
									r_number_rx_done <= 1'b0;	
    			end
		endcase
	end																															

end
										 			  

								  						  
always @(posedge i_sclk or negedge i_nreset) begin
	if(!i_nreset) begin										  
					d_spi_cse <= 1'b0;
					d_r_rdat_rx_done <= 1'b0;
	end
    else begin	 d_r_rdat_rx_done <= r_rdat_rx_done;		 //   done  (r_data receiving)		
	                     d_spi_cse <= i_spi_cse;
	end
end


//=========================================================================


//--------------------------------------------
// ### Parallel data bit shift control ###	 
// ### Parallel data to Serial output ###
//--------------------------------------------


always @(posedge i_sclk or negedge i_nreset) begin
	if(!i_nreset) 		r_tdat_tx_rdat  <=  8'b0;
	else if (	i_spi_cse ==  p_cse_pol)	
		r_tdat_tx_rdat	 <= 8'b0;			
	else if(i_tdat_input_en  )    
		  r_tdat_tx_rdat	 <= i_tdat_tx_rdat;
	else 												   
	      r_tdat_tx_rdat	 <= r_tdat_tx_rdat;		
end


always @(posedge i_sclk or negedge i_nreset) begin
	if(!i_nreset) 		r_p2s_tdat_reg <= 8'b0;	
	else if (	i_spi_cse ==  p_cse_pol)	
		r_p2s_tdat_reg <=8'b0 ;
	else 	  begin
		    case (C_ST)
			
			NUMBER : if(r_bit_cnt ==4'b0111 & (~TX_RX_NST_info)  & w_cap_en)				                
				                r_p2s_tdat_reg <= r_tdat_tx_rdat;   
							 else    r_p2s_tdat_reg <= r_p2s_tdat_reg; 
			TXDATA :	    if(w_chg_en)
                            if(r_bit_cnt == p_dat_wth)
                                       r_p2s_tdat_reg <= r_tdat_tx_rdat;                            
                            else    r_p2s_tdat_reg <= r_p2s_tdat_reg << 1'b1;
                            else    r_p2s_tdat_reg <= r_p2s_tdat_reg; 
			default :	r_p2s_tdat_reg <= 8'b0; 
		 endcase
    end	 
end		  


always @(C_ST or r_p2s_tdat_reg  ) begin	   
	case (C_ST)	   	
	  TXDATA :			o_spi_sdo <=  r_p2s_tdat_reg[7];						
	   default : 		o_spi_sdo  <= 1'b0;
	endcase
end


//--------------------------------------------
// ### Serial input data to Parallel control ###
//--------------------------------------------
always @(posedge i_sclk or negedge i_nreset) begin
   if(!i_nreset) begin	
	            
				r_s2p_number_reg  <= 8'b0;
 				r_s2p_addr_reg <= 8'b0;
				r_s2p_rdat_reg <= 8'b0;
			  end								  
   else if(w_sl_end_sync) begin   
	                r_s2p_number_reg  <= 8'b0;
 					r_s2p_addr_reg <= 8'b0;
					r_s2p_rdat_reg <=  8'b0;
   end
   
   else if(w_cap_en) begin		  //DATA RECEIVE in falling edge  
	case (C_ST)
		
		NUMBER :
			r_s2p_number_reg <=  {r_s2p_number_reg[6:0], i_spi_sdi};
		
		ADDR : 
			 r_s2p_addr_reg <=      {r_s2p_addr_reg[6:0], i_spi_sdi};				

		RXDATA :																									
			 r_s2p_rdat_reg <=       {r_s2p_rdat_reg[ 6:0], i_spi_sdi};		

	    default :	begin	r_s2p_number_reg <= 8'b0;
		                            r_s2p_addr_reg <= 8'b0;
               			            r_s2p_rdat_reg <= 8'b0;
				 end
	endcase
   end
   
   else begin  r_s2p_number_reg <= r_s2p_number_reg;
	                 r_s2p_addr_reg <= r_s2p_addr_reg;
                     r_s2p_rdat_reg <= r_s2p_rdat_reg;
	end
end			   	   



always @(posedge i_sclk or negedge i_nreset) begin
	
	  if(!i_nreset) 	  r_number_rx <= 8'b0; 
	 else 	  
	  case (C_ST)	 		
		IDLE  :         r_number_rx <= 8'b0; 
		NUMBER :	    if(r_number_rx_done & ~(r_s2p_number_reg == 8'b0))				                     
			                      r_number_rx <= {1'b0 , r_s2p_number_reg[6:0] -1'b1};  	   //the number of  Burst  register
		                   else  r_number_rx  <= r_number_rx ;					    		
		default : 	  r_number_rx <= r_number_rx; 
	  endcase		
end


//--------------------------------------------
// ###  address out  to read & write ###
// ## # data request to serial data out
//--------------------------------------------		
 always @(posedge i_sclk or negedge i_nreset) begin
   if(!i_nreset) 	  begin
	    r_addr_rx <= 8'b0;			
	    o_addr <= 1'b0;	  end
  else 	   			   	          			   
     case (C_ST)
		IDLE   :  	r_addr_rx <= 8'b0;																	  //////////////////////
		DONE :	    r_addr_rx   <=8'b0;
		ADDR :	    if(r_addr_rx_done)	r_addr_rx <= r_s2p_addr_reg ;  
		                else	 r_addr_rx <= r_addr_rx;					    		
		default : 	r_addr_rx <= r_addr_rx; 
	endcase		
	
	case (C_ST)
	  TXDATA  :    o_addr  <=   r_addr_rx +	  r_sl_word_no2;
	  RXDATA  :    o_addr  <=   r_addr_rx +	  r_sl_word_no;
	  default :   o_addr  <=   r_addr_rx ;	
	endcase 
	
 end 
  						 

 always @(posedge i_sclk or negedge i_nreset) begin	 	 
   if(!i_nreset) 
	      TX_RX_NST_info <= 8'b0;
   else 	 
    	   if (i_spi_cse == p_cse_pol) 	 
		      TX_RX_NST_info <= 8'b0;
	       else if((C_ST == NUMBER)& (r_bit_cnt  == 4'b0010 )& w_cap_en ) 														
		      TX_RX_NST_info <= r_s2p_number_reg[1];
		  else 							
			  TX_RX_NST_info <= TX_RX_NST_info;	   
end 	 
		 
			 				    	                       				   

always @(posedge i_sclk or negedge i_nreset) begin	 	 
     if(!i_nreset) 
	    o_tdat_tx_req <= 8'b0; 	
	 else if  (((C_ST==TXDATA)& (r_sl_word_no < r_number_rx)) | ((C_ST== NUMBER) & (~TX_RX_NST_info)) ) 		    
		  if(  (r_bit_cnt == 4'b0011 ) && w_chg_en   ) 						
			         o_tdat_tx_req <= 1'b1;	  
		    else  o_tdat_tx_req <= 1'b0; 
        else      o_tdat_tx_req <= 1'b0; 	
end			 
										 

always @(C_ST or r_rdat_rx_done or r_s2p_rdat_reg) begin	
	if(!i_nreset)											
		o_rdat_rx <= 8'b0;
	else 	
	case (C_ST)
		RXDATA :	if((r_bit_cnt == p_dat_wth) & w_cap_en ) 	o_rdat_rx <= r_s2p_rdat_reg;
				   else	            			o_rdat_rx <= o_rdat_rx;	              
		default : 				o_rdat_rx <= 8'b0;
	endcase
end	

assign	o_rdat_rx_wen = (r_rdat_rx_done && ~d_r_rdat_rx_done) ? 1'b1 : 1'b0;



//--------------------------------------------
// ### Slave common status signal ###
//--------------------------------------------

always @(posedge i_sclk or negedge i_nreset) begin
	if(!i_nreset) 	begin
		 r_error  <=  1'b0;		
		 r_done  <=  1'b0;	
		end 
    
	else  begin								
		
		if ( (N_ST == DONE) & ( w_chg_en))											//    error   check
		     r_error  <= 1'b1;
		else if (	(d_spi_cse == ~ p_cse_pol) & (i_spi_cse ==  p_cse_pol) &
			        ~((N_ST == IDLE) || (N_ST == DONE)) )
		     r_error  <= 1'b1;		
		else if  ((d_spi_cse == p_cse_pol) & (i_spi_cse == ~p_cse_pol))   
		     r_error  <=  1'b0;				     													   		  
		else 
			 r_error <= r_error;	
		 
		 
	   	 if  ((d_spi_cse == p_cse_pol) & (i_spi_cse == ~p_cse_pol))   
		   	  r_done  <=  1'b0;		
		 else 
			  r_done <=  (N_ST == DONE )? 1'b1: r_done;
     end		
end 	 

	
assign	o_done =  r_done;
assign	o_busy    =  ((C_ST == IDLE) || (C_ST == DONE)) ? 1'b0 : 1'b1;	 
assign o_error   = r_error; 																	  
																						   

//=============================================================================	  

endmodule


//=============================================================================