register_arr.v

来自「spi slave 8bit address 1bit r/w 7bit num」· Verilog 代码 · 共 32 行

module register_arr #(parameter DATASIZE = 8, parameter ADDRSIZE = 8)
	// Memory data word width // Number of mem address bits
(
output [DATASIZE-1:0] rdata,
output out_valid,
 input [DATASIZE-1:0]  wdata,
 input [ADDRSIZE-1:0]  waddr, raddr,
 input wr_en , r_en , clk);
 
reg [DATASIZE-1:0] mem[ADDRSIZE-1:0]; // 256 words * 8-bit memory
reg [DATASIZE-1:0] rdata  ;		   
reg out_valid;

always @(posedge clk) begin
if (r_en )  begin rdata <= mem[raddr]; 
	out_valid<=1'b1;
	end
else begin
	rdata = 8'h0; 
	out_valid<=1'b0;
end	   
end
	

always @(posedge clk)
if (wr_en ) mem[waddr] <= wdata;

endmodule