iostm8a.h

cxstm8 编译器

/*	IO DEFINITIONS FOR STM8 A61/A51 family
 *	Copyright (c) 2008 by COSMIC Software
 */

/*	PORTS section
 */
/*	Port A
 */
volatile char PA_ODR        @0x5000;	/* Data Output Latch reg */
volatile char PA_IDR        @0x5001;	/* Input Pin Value reg */
volatile char PA_DDR        @0x5002;	/* Data Direction */
volatile char PA_CR1        @0x5003;	/* Control register 1 */
volatile char PA_CR2        @0x5004;	/* Control register 2 */

/*	Port B
 */
volatile char PB_ODR        @0x5005;	/* Data Output Latch reg */
volatile char PB_IDR        @0x5006;	/* Input Pin Value reg */
volatile char PB_DDR        @0x5007;	/* Data Direction */
volatile char PB_CR1        @0x5008;	/* Control register 1 */
volatile char PB_CR2        @0x5009;	/* Control register 2 */

/*	Port C
 */
volatile char PC_ODR        @0x500a;	/* Data Output Latch reg */
volatile char PC_IDR        @0x500b;	/* Input Pin Value reg */
volatile char PC_DDR        @0x500c;	/* Data Direction */
volatile char PC_CR1        @0x500d;	/* Control register 1 */
volatile char PC_CR2        @0x500e;	/* Control register 2 */

/*	Port D
 */
volatile char PD_ODR        @0x500f;	/* Data Output Latch reg */
volatile char PD_IDR        @0x5010;	/* Input Pin Value reg */
volatile char PD_DDR        @0x5011;	/* Data Direction */
volatile char PD_CR1        @0x5012;	/* Control register 1 */
volatile char PD_CR2        @0x5013;	/* Control register 2 */

/*	Port E
 */
volatile char PE_ODR        @0x5014;	/* Data Output Latch reg */
volatile char PE_IDR        @0x5015;	/* Input Pin Value reg */
volatile char PE_DDR        @0x5016;	/* Data Direction */
volatile char PE_CR1        @0x5017;	/* Control register 1 */
volatile char PE_CR2        @0x5018;	/* Control register 2 */

/*	Port F
 */
volatile char PF_ODR        @0x5019;	/* Data Output Latch reg */
volatile char PF_IDR        @0x501a;	/* Input Pin Value reg */
volatile char PF_DDR        @0x501b;	/* Data Direction */
volatile char PF_CR1        @0x501c;	/* Control register 1 */
volatile char PF_CR2        @0x501d;	/* Control register 2 */

/*	Port G
 */
volatile char PG_ODR        @0x501e;	/* Data Output Latch reg */
volatile char PG_IDR        @0x501f;	/* Input Pin Value reg */
volatile char PG_DDR        @0x5020;	/* Data Direction */
volatile char PG_CR1        @0x5021;	/* Control register 1 */
volatile char PG_CR2        @0x5022;	/* Control register 2 */

/*	Port H
 */
volatile char PH_ODR        @0x5023;	/* Data Output Latch reg */
volatile char PH_IDR        @0x5024;	/* Input Pin Value reg */
volatile char PH_DDR        @0x5025;	/* Data Direction */
volatile char PH_CR1        @0x5026;	/* Control register 1 */
volatile char PH_CR2        @0x5027;	/* Control register 2 */

/*	Port I
 */
volatile char PI_ODR        @0x5028;	/* Data Output Latch reg */
volatile char PI_IDR        @0x5029;	/* Input Pin Value reg */
volatile char PI_DDR        @0x502a;	/* Data Direction */
volatile char PI_CR1        @0x502b;	/* Control register 1 */
volatile char PI_CR2        @0x502c;	/* Control register 2 */

/*	FLASH section
 */
volatile char FLASH_CR1     @0x505a;	/* Flash Control Register 1 */
volatile char FLASH_CR2     @0x505b;	/* Flash Control Register 2 */
volatile char FLASH_NCR2    @0x505c;	/* Flash Complementary Control Reg 2 */
volatile char FLASH_FPR     @0x505d;	/* Flash Protection reg */
volatile char FLASH_NFPR    @0x505e;	/* Flash Complementary Protection reg */
volatile char FLASH_IAPSR   @0x505f;	/* Flash in-appl Prog. Status reg */
volatile char FLASH_PUKR    @0x5062;	/* Flash Program memory unprotection reg */
volatile char FLASH_DUKR    @0x5064;	/* Data EEPROM unprotection reg */

/*	External Interrupt Controller section
 */
volatile char EXTI_CR1      @0x50a0;	/* Ext Int Ctrl reg 1 */
volatile char EXTI_CR2      @0x50a1;	/* Ext Int Ctrl reg 2 */

/*	RSTC section
 */
volatile char RST_SR        @0x50b3;	/* Reset Status register */

/*	CLOCK section
 */
volatile char CLK_ICKCR     @0x50c0;	/* Internal Clock Control reg */
volatile char CLK_ECKCR     @0x50c1;	/* External Clock Control reg */
volatile char CLK_CMSR      @0x50c3;	/* Master Status reg */
volatile char CLK_SWR       @0x50c4;	/* Master Switch reg */
volatile char CLK_SWCR      @0x50c5;	/* Switch Control reg */
volatile char CLK_CKDIVR    @0x50c6;	/* Divider register */
volatile char CLK_PCKENR1   @0x50c7;	/* Peripheral Clock Gating reg 1 */
volatile char CLK_CSSR      @0x50c8;	/* Security System register */
volatile char CLK_CCOR      @0x50c9;	/* Configurable Clock Ctrl reg */
volatile char CLK_PCKENR2   @0x50ca;	/* Peripheral Clock Gating reg 2 */
volatile char CLK_CANCCR    @0x50cb;	/* Can Clock Control reg */
volatile char CLK_HSITRIMR  @0x50cc;	/* HSI Calibration Trimming reg */
volatile char CLK_SWIMCCR   @0x50cd;	/* SWIM Clock Control reg */

/*	WATCHDOG section
 */
volatile char WWDG_CR       @0x50d1;	/* WWDG Control register */
volatile char WWDG_WR       @0x50d2;	/* WWDG Window register */
volatile char IWDG_KR       @0x50e0;	/* IWDG Key register */
volatile char IWDG_PR       @0x50e1;	/* IWDG Prescaler register */
volatile char IWDG_RLR      @0x50e2;	/* IWDG Reload register */

/*	AWU section
 */
volatile char AWU_CSR1      @0x50f0;	/* AWU Control/Status reg 1 */
volatile char AWU_APR       @0x50f1;	/* AWU Async Prescale Buffer reg */
volatile char AWU_TBR       @0x50f2;	/* AWU Timebase selection reg */
volatile char BEEP_CSR      @0x50f3;	/* BEEP control/status reg */

/*	SPI section
 */
volatile char SPI_CR1       @0x5200;	/* SPI Control register 1 */
volatile char SPI_CR2       @0x5201;	/* SPI Control register 2 */
volatile char SPI_ICR       @0x5202;	/* SPI Interrupt/Ctrl reg */
volatile char SPI_SR        @0x5203;	/* SPI Status register */
volatile char SPI_DR        @0x5204;	/* SPI Data I/O reg */
volatile char SPI_CRCPR     @0x5205;	/* SPI CRC Polynomial reg */
volatile char SPI_RXCRCR    @0x5206;	/* SPI Rx CRC register */
volatile char SPI_TXCRCR    @0x5207;	/* SPI Tx CRC register */

/*	I2C section
 */
volatile char I2C_CR1       @0x5210;	/* Control register 1 */
volatile char I2C_CR2       @0x5211;	/* Control register 2 */
volatile char I2C_FREQR     @0x5212;	/* Frequency register */
volatile char I2C_OARL      @0x5213;	/* Own Address reg low */
volatile char I2C_OARH      @0x5214;	/* Own Address reg high */
volatile char I2C_DR        @0x5216;	/* Data Register */
volatile char I2C_SR1       @0x5217;	/* Status Register 1 */
volatile char I2C_SR2       @0x5218;	/* Status Register 2 */
volatile char I2C_SR3       @0x5219;	/* Status Register 3 */
volatile char I2C_ITR       @0x521a;	/* Interrupt Control reg */
volatile char I2C_CCRL      @0x521b;	/* Clock Control reg low */
volatile char I2C_CCRH      @0x521c;	/* Clock Control reg high */
volatile char I2C_TRISER    @0x521d;	/* Trise reg */
volatile char I2C_PECR      @0x521e;	/* Packet Error Checking reg */

/*	USART section
 */
volatile char USART_SR      @0x5230;	/* Status register */
volatile char USART_DR      @0x5231;	/* Data register */
volatile char USART_BRR1    @0x5232;	/* Baud Rate reg 1 */
volatile char USART_BRR2    @0x5233;	/* Baud Rate reg 2 */
volatile char USART_CR1     @0x5234;	/* Control register 1 */
volatile char USART_CR2     @0x5235;	/* Control register 2 */
volatile char USART_CR3     @0x5236;	/* Control register 3 */
volatile char USART_CR4     @0x5237;	/* Control register 4 */
volatile char USART_CR5     @0x5238;	/* Control register 5 */
volatile char USART_GTR     @0x5239;	/* Guard Time register */
volatile char USART_PSCR    @0x523a;	/* Prescaler register */