top_cdr.v

来自「Clock data recovery .........good exampl」· Verilog 代码 · 共 50 行

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2003 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Application : XAPP868
//  /   /         Filename: top_cdr.v
// /___/   /\     Timestamp: Thu Jan 17 2008
// \   \  /  \
//  \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module top_cdr(DT_IN, DT_OUT, SPEED_SEL, CLK, RST, SAMPLE_EN, TST_CLK_OUT);
   input       DT_IN;
   output      DT_OUT;
   input       SPEED_SEL;
   input       CLK;
   input       RST;
   output      SAMPLE_EN;
   output      TST_CLK_OUT;
   
   
   wire [19:0] ctrl;
   wire [15:0] phase;
   wire        sample_phase;
   wire        phase_valid;
   wire[31:0]  center_f;
   wire        sample_en_int;
   wire        sample_90_int;
   
   assign SAMPLE_EN = sample_90_int;
   
   
   vco Inst_vco(.CTRL(ctrl[12:0]), .CENTER_F(center_f), .CLK(CLK), .RST(RST), .SAMPLE_PHASE(sample_phase), .PHASE(phase), .TST_MSB(TST_CLK_OUT), .PHASE_VALID(phase_valid), .SAMPLE_EN(sample_en_int), .SAMPLE_90(sample_90_int));
      
   lp_filter  Inst_filter(.G1(5'b10011), .G2(5'b00011), .PHASE_IN(phase), .PHASE_VALID(phase_valid), .CTRL(ctrl), .CLK(CLK), .RST(RST));
      
   DATASAMPLER Inst_DATASAMPLER(.CLK(CLK), .RST(RST), .DATA_IN(DT_IN), .SAMPLE_ENABLE(sample_90_int), .DTOUT(DT_OUT));
      
   TRAN_DETECT Inst_TRAN_DETECT(.CLK(CLK), .RST(RST), .DATA_IN(DT_IN), .DDATA_OUT(), .S_ENABLE(sample_phase));
   
   assign center_f = (SPEED_SEL == 1'b1) ? (32'h037EB204) : 
                     (32'h02A2957A);
	
endmodule