vio_xst_example.v

来自「Clock data recovery .........good exampl」· Verilog 代码 · 共 62 行

//-----------------------------------------------------------------------------
// Copyright (c) 1999-2006 Xilinx Inc.  All rights reserved.
//-----------------------------------------------------------------------------
// Title      : Virtual I/O Core Xilinx XST Usage Example
// Project    : ChipScope
//-----------------------------------------------------------------------------
// File       : vio_xst_example.v
// Company    : Xilinx Inc.
// Created    : 2002/11/26
//-----------------------------------------------------------------------------
// Description: Example of how to instantiate the VIO core in a Verilog 
//              design for use with the Xilinx XST synthesis tool.
//-----------------------------------------------------------------------------

module vio_xst_example
  (
  );


  //-----------------------------------------------------------------
  //
  //  VIO Core wire declarations
  //
  //-----------------------------------------------------------------
  wire [35:0] control;
  wire [1:0] async_in;
  wire [63:0] async_out;


  //-----------------------------------------------------------------
  //
  //  VIO core instance
  //
  //-----------------------------------------------------------------
  vio i_vio
    (
      .control(control),
      .async_in(async_in),
      .async_out(async_out)
    );


endmodule


//-------------------------------------------------------------------
//
//  VIO core module declaration
//
//-------------------------------------------------------------------
module vio
  (
    control,
    async_in,
    async_out
  );
  input  [35:0] control;
  input  [1:0] async_in;
  output [63:0] async_out;
endmodule