vio_xst_verilog_example.arg

Clock data recovery .........good example

#
# Usage: generate.exe vio_example -f=<arg_file_name>
#
-tool=xst
-language=Verilog
-outputdirectory=C:\ISE_designs\CDRE1T1\Verilog_version\code\cspro
-compname=vio
-asyncinwidth=2
-asyncoutwidth=64