top_level.v

Clock data recovery .........good example

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2003 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Application : XAPP868
//  /   /         Filename: top_level.v
// /___/   /\     Timestamp: Thu Jan 17 2008
// \   \  /  \
//  \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////

module top_level(CLK_P, CLK_N, DT1, DT2, DTE, CKE);
   input        CLK_P;
   input        CLK_N;
   output       DT1;
   output       DT2;
   output [1:0] DTE;
   output [1:0] CKE;
   
   
   wire [1:0]   speed_sel;
   wire [1:0]   clk2m;
   wire [1:0]   prbs;
   wire [1:0]   rec_clk2m;
   wire [1:0]   speed_sel_cdr;
   wire [1:0]   dt_out;
   wire [1:0]   err;
   wire [1:0]   err_rst;
   wire [1:0]   dt_cdr_in;
   wire         sel_1;
   wire         sel_2;
   wire [1:0]   dt_en;
   wire [1:0]   en;
   wire         clk;
   wire [12:0]  ctrl_0;
   wire [12:0]  ctrl_1;
   wire [35:0]  control0;
   wire [1:0]   async_in;
   wire [63:0]  async_out;
   wire         RST;
   wire [31:0]  center_f0;
   wire [31:0]  center_f1;
   
   assign CKE = rec_clk2m;
   assign DTE[0] = dt_out[0];
   assign DTE[1] = dt_out[1];
   
   
   assign dt_cdr_in[0] = (sel_1 == 1'b0) ? prbs[0] : 
                         prbs[1];
   
   assign dt_cdr_in[1] = (sel_2 == 1'b0) ? prbs[1] : 
                         prbs[0];
   
   
   IBUFGDS ibufgds_i(.O(clk), .I(CLK_P), .IB(CLK_N));
   
   
   vco Inst_vco_1(.CTRL(ctrl_0), .CENTER_F(center_f0), .CLK(clk), .RST(RST), .SAMPLE_PHASE(1'b0), .PHASE(), .PHASE_VALID(), .TST_MSB(clk2m[0]), .SAMPLE_90(), .SAMPLE_EN(dt_en[0]));
   
   
   vco Inst_vco_2(.CTRL(ctrl_1), .CENTER_F(center_f1), .CLK(clk), .RST(RST), .SAMPLE_PHASE(1'b0), .PHASE(), .PHASE_VALID(), .TST_MSB(clk2m[1]), .SAMPLE_90(), .SAMPLE_EN(dt_en[1]));
   
   
   prbsgen Inst_prbsgen_1(.CLK(clk), .EN(dt_en[0]), .RST(RST), .PRBSOUT(prbs[0]));
   
   
   prbsgen Inst_prbsgen_2(.CLK(clk), .EN(dt_en[1]), .RST(RST), .PRBSOUT(prbs[1]));
   
   
   top_cdr Inst_top_cdr_1(.DT_IN(dt_cdr_in[0]), .DT_OUT(dt_out[0]), .SPEED_SEL(speed_sel_cdr[0]), .CLK(clk), .RST(RST), .SAMPLE_EN(en[0]), .TST_CLK_OUT(rec_clk2m[0]));
   
   
   top_cdr Inst_top_cdr_2(.DT_IN(dt_cdr_in[1]), .DT_OUT(dt_out[1]), .SPEED_SEL(speed_sel_cdr[1]), .CLK(clk), .RST(RST), .SAMPLE_EN(en[1]), .TST_CLK_OUT(rec_clk2m[1]));
   
   
   prbschk Inst_prbschk_1(.CLK2M(clk), .EN(en[0]), .RST(RST), .ERR(err[0]), .ERR_RST(err_rst[0]), .RT_ERR(), .PRBSIN(dt_out[0]));
   
   
   prbschk Inst_prbschk_2(.CLK2M(clk),  .EN(en[1]), .RST(RST), .ERR(err[1]), .ERR_RST(err_rst[1]), .RT_ERR(), .PRBSIN(dt_out[1]));
   
   
   icon i_icon(.control0(control0));
   
   
   vio i_vio(.control(control0), .async_in(async_in), .async_out(async_out));
   
   assign ctrl_0 = async_out[12:0];
   assign ctrl_1 = async_out[25:13];
   assign speed_sel = async_out[27:26];
   assign sel_1 = async_out[28];
   assign sel_2 = async_out[29];
   assign speed_sel_cdr = async_out[31:30];
   assign err_rst = async_out[33:32];
   assign RST = async_out[34];
   assign async_in[1:0] = err;
	
	assign center_f0 = (speed_sel[0] == 1'b1) ? (32'h037EB204) : 
                     (32'h02A2957A);
	assign center_f1 = (speed_sel[1] == 1'b1) ? (32'h037EB204) : 
                     (32'h02A2957A);
   
endmodule