datasampler.v

来自「Clock data recovery .........good exampl」· Verilog 代码 · 共 54 行

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2003 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Application : XAPP868
//  /   /         Filename: datasampler.v
// /___/   /\     Timestamp: Thu Jan 17 2008
// \   \  /  \
//  \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps


module DATASAMPLER(CLK, RST, DATA_IN, SAMPLE_ENABLE, DTOUT);
   input     CLK;
   input     RST;
   input     DATA_IN;
   input     SAMPLE_ENABLE;
   output    DTOUT;
   
   reg [5:0] delay;
   reg       sampled;
   
   assign DTOUT = sampled;
   
   
   always @(posedge CLK or negedge RST)
      if (RST == 1'b0)
         sampled <= 1'b0;
      else 
      begin
         if (SAMPLE_ENABLE == 1'b1)
            sampled <= delay[2];
      end
   
   
   always @(posedge CLK or negedge RST)
      if (RST == 1'b0)
         delay <= {6{1'b0}};
      else 
      begin
         delay[0] <= DATA_IN;
         delay[5:1] <= delay[4:0];
      end
   
endmodule