tb_cdr.v

Clock data recovery .........good example

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2003 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Application : XAPP868
//  /   /         Filename: tb_cdr.v
// /___/   /\     Timestamp: Thu Jan 17 2008
// \   \  /  \
//  \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps


module tb_cdr;

	// Inputs
	reg DT_IN;
	reg SPEED_SEL;
	reg CLK;
	reg RST;
	reg [12:0] ctrl_0;
	reg [31:0] CENTER_F;

	// Outputs
	wire DT_OUT;
	wire SAMPLE_EN;
	wire TST_CLK_OUT;
	wire [63:0] out_f;
	wire [63:0] out_ph1;
	wire dt_en;

	// Instantiate the Unit Under Test (UUT)
	top_cdr uut (
		.DT_IN(prbsdata), 
		.DT_OUT(DT_OUT), 
		.SPEED_SEL(SPEED_SEL), 
		.CLK(CLK), 
		.RST(RST), 
		.SAMPLE_EN(SAMPLE_EN), 
		.TST_CLK_OUT(TST_CLK_OUT)
	);

   
   ph_meter inst_ph_meter(.in_sig_1(TST_CLK_OUT), .in_sig_2(clk_drv));
   
   vco inst_vco_1(.CTRL(ctrl_0), .CENTER_F(CENTER_F), .CLK(CLK), .RST(RST), .SAMPLE_PHASE(1'b0), .PHASE(), .PHASE_VALID(), .TST_MSB(clk_drv), .SAMPLE_90(), .SAMPLE_EN(dt_en));
   
   prbsgen inst_prbsgen_1 (.CLK(CLK), .EN(dt_en), .RST(RST), .PRBSOUT(prbsdata));

   prbschk inst_prbschk (.CLK2M(CLK), .EN(SAMPLE_EN), .RST(RST), .ERR(), .ERR_RST(1'b0), .RT_ERR(), .PRBSIN (DT_OUT));

	initial begin
		// Initialize Inputs
		DT_IN = 0;
		SPEED_SEL = 1;
		CENTER_F = 32'h037EB204;
		CLK = 0;
		RST = 1;
		ctrl_0 = 0000000000001;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		ctrl_0 = 13'b0000000000010;
		RST=0;
		#10000;
		ctrl_0= 13'b0000000000010;
		RST=1;
		SPEED_SEL=1;
		#200000000;
		RST=1;
		ctrl_0= 13'b0100000000010;
		#200000000;
		ctrl_0= 13'b0000000000000;
		
	end
     
	always	begin
#3.333 assign CLK=~(CLK);
	end 
endmodule