top_cdr.vhd

Clock data recovery .........good example

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.0
--  \   \        Filename: top_cdr.vhd
--  /   /        Date Last Modified:  Thu Jan 17 2008
-- /___/   /\    Date Created: Wed May 2 2007
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: This is the top level of the CDR 
--         
--         
--Revision History:
--    Rev 1.0 - First created, P. Novellini and G. Guasti, Wed May 2 2007.
------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- TO ELISA
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity top_cdr is
    Port ( DT_IN : in  STD_LOGIC;
           DT_OUT : out  STD_LOGIC;
           SPEED_SEL : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
	   RST : in  STD_LOGIC;
	   SAMPLE_EN: out STD_LOGIC;
           TST_CLK_OUT : out  STD_LOGIC);
end top_cdr;

architecture Behavioral of top_cdr is

--START COMPONENT DECLARATION
COMPONENT vco
	PORT(
		CTRL : IN std_logic_vector(12 downto 0);
		CENTER_F : IN STD_LOGIC_VECTOR (31 downto 0);
		CLK : IN std_logic;
		RST : IN std_logic;
		SAMPLE_PHASE : IN std_logic;          
		PHASE : OUT std_logic_vector(15 downto 0);
		PHASE_VALID : OUT std_logic;
		TST_MSB: out std_logic;
		SAMPLE_90 : OUT std_logic;
		SAMPLE_EN : OUT std_logic
		);
END COMPONENT;

COMPONENT lp_filter
	PORT(
		G1 : IN std_logic_vector(4 downto 0);
		G2 : IN std_logic_vector(4 downto 0);
		PHASE_IN : IN std_logic_vector(15 downto 0);
		PHASE_VALID : IN std_logic;
		CLK : IN std_logic;
		RST : IN std_logic;          
		CTRL : OUT std_logic_vector(19 downto 0)
		);
END COMPONENT;

COMPONENT TRAN_DETECT
	PORT(
		CLK : IN std_logic;
		RST : IN std_logic;
		DATA_IN : IN std_logic;          
		DDATA_OUT : OUT std_logic;
		S_ENABLE : OUT std_logic
		);
END COMPONENT;

COMPONENT DATASAMPLER
	PORT(
		CLK : IN std_logic;
		RST : IN std_logic;
		DATA_IN : IN std_logic;
		SAMPLE_ENABLE : IN std_logic;          
		DTOUT : OUT std_logic
		);
	END COMPONENT;	
	
signal ctrl: std_logic_vector(19 downto 0);
signal phase: std_logic_vector(15 downto 0);
signal center_f: std_logic_vector (31 downto 0);
signal sample_phase, phase_valid, sample_en_int, sample_90_int : std_logic;

begin

SAMPLE_EN <= sample_90_int;
center_f<=(x"037EB204") when SPEED_SEL='1'else (x"02A2957A");

Inst_vco: vco PORT MAP(
		CTRL => ctrl(12 downto 0),
		CENTER_F => center_f,
		CLK => CLK,
		RST => RST,
		SAMPLE_PHASE => sample_phase,
		PHASE => phase,
		TST_MSB=> TST_CLK_OUT,
		PHASE_VALID => phase_valid,
		SAMPLE_EN => sample_en_int,
		SAMPLE_90 => sample_90_int
	);
	
Inst_filter: lp_filter PORT MAP(
		G1 => b"10011",
		G2 => b"00011",
		PHASE_IN => phase,
		PHASE_VALID => phase_valid,
		CTRL => ctrl,
		CLK => CLK,
		RST => RST
	);
	
Inst_DATASAMPLER: DATASAMPLER PORT MAP(
		CLK => CLK,
		RST => RST,
		DATA_IN => DT_IN,
		SAMPLE_ENABLE => sample_90_int,
		DTOUT => DT_OUT
	);

Inst_TRAN_DETECT: TRAN_DETECT PORT MAP(
		CLK => CLK,
		RST => RST,
		DATA_IN => DT_IN,
		DDATA_OUT => open,
		S_ENABLE => sample_phase
	);
	
end Behavioral;