datasampler.vhd

来自「Clock data recovery .........good exampl」· VHDL 代码 · 共 69 行

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.0
--  \   \        Filename: datasampler.vhd
--  /   /        Date Last Modified:  Thu Jan 17 2008
-- /___/   /\    Date Created: Wed May 2 2007
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: This is block sempling the data
--         
--         
--Revision History:
--    Rev 1.0 - First created, P. Novellini and G. Guasti, Wed May 2 2007.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity DATASAMPLER is
port
(
    CLK				: in    std_logic;      
    RST				: in    std_logic;
    DATA_IN			: in    std_logic;
    SAMPLE_ENABLE	: in    std_logic;      
    DTOUT			: out   std_logic     
); 
end DATASAMPLER;

architecture RTL of DATASAMPLER is
    signal  delay		:   std_logic_vector(5 downto 0);
    signal  sampled		:   std_logic;
begin

    DTOUT    <=   sampled;

    process( CLK, RST ) 
    begin
            if RST='0' then
                sampled <= '0';
            elsif (CLK'event and CLK = '1') then
                if SAMPLE_ENABLE = '1' then
                	sampled <= delay(2);
                end if;
            end if;
    end process;

    process( CLK, RST ) 
    begin
            if RST='0' then
                delay <= (others=>'0');
            elsif (CLK'event and CLK = '1') then
                delay(0) <= DATA_IN;
                delay(5 downto 1) <= delay(4 downto 0);
            end if;
    end process;

end RTL;