tran_detect.vhd

Clock data recovery .........good example

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.0
--  \   \        Filename: tran_detect.vhd
--  /   /        Date Last Modified:  Thu Jan 17 2008
-- /___/   /\    Date Created: Wed May 2 2007
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: This is the transition detector in the PLL 
--         
--         
--Revision History:
--    Rev 1.0 - First created, P. Novellini and G. Guasti, Wed May 2 2007.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity TRAN_DETECT is
port
(
    CLK				: in    std_logic;      
    RST				: in    std_logic;
    DATA_IN			: in    std_logic;      
    DDATA_OUT		: out   std_logic; -- delayed output data      
    S_ENABLE		: out   std_logic -- enable the sampling of the phase     
); 
end TRAN_DETECT;

architecture RTL of TRAN_DETECT is
    signal  dinreg		:   std_logic_vector(1 downto 0);
    signal  d2_xor_d3	:   std_logic;
begin

    d2_xor_d3    <=   dinreg(0) xor dinreg(1);
    							
    process( CLK, RST ) 
    begin
            if RST='0' then
                S_ENABLE <= '0';
                DDATA_OUT <= '0';
                dinreg <= (others=>'0');
            elsif (CLK'event and CLK = '1') then
                dinreg(0) <= DATA_IN;
                dinreg(1) <= dinreg(0);
                S_ENABLE <= d2_xor_d3;
                DDATA_OUT <= dinreg(1);
            end if;
    end process;
end RTL;