top_level.vhd

Clock data recovery .........good example

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.0
--  \   \        Filename: top_level.vhd
--  /   /        Date Last Modified:  Thu Jan 17 2008
-- /___/   /\    Date Created: Wed May 2 2007
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: This is the top level of the demo design 
--         
--         
--Revision History:
--    Rev 1.0 - First created, P. Novellini and G. Guasti, Wed May 2 2007.
------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


library UNISIM;
use UNISIM.VComponents.all;

entity top_level is
    Port ( CLK_P, CLK_N : in  STD_LOGIC;
           --RST : in  STD_LOGIC;
           DT1 : out  STD_LOGIC;
           DT2 : out  STD_LOGIC;
           DTE : out  STD_LOGIC_VECTOR(1 downto 0);
           CKE : out  STD_LOGIC_VECTOR(1 downto 0));
end top_level;

architecture Behavioral of top_level is

--START COMPONENT DECLARATION

 	component icon
    	port(
      		control0    :   out std_logic_vector(35 downto 0)
    	);
  	end component;
  	
  	component vio
    	port(
      		control     : in    std_logic_vector(35 downto 0);
      		async_in    : in    std_logic_vector(1 downto 0);
      		async_out   :   out std_logic_vector(63 downto 0)
    	);
  	end component;

	COMPONENT IBUFGDS
	PORT
	(
    		O  : out std_logic;
    		I  : in  std_logic;
    		IB : in  std_logic
	);
	end component;

	COMPONENT vco
	PORT(
		CTRL : IN std_logic_vector(12 downto 0);
		CENTER_F: std_logic_vector (31 downto 0);
		CLK : IN std_logic;
		RST : IN std_logic;
		SAMPLE_PHASE : IN std_logic;          
		PHASE : OUT std_logic_vector(15 downto 0);
		PHASE_VALID : OUT std_logic;
		TST_MSB : OUT std_logic;
		SAMPLE_90 : OUT std_logic;
		SAMPLE_EN : OUT std_logic
		);
	END COMPONENT;

	COMPONENT prbsgen
	PORT(
		CLK : IN std_logic;
		EN :IN std_logic;
		RST : IN std_logic;          
		PRBSOUT : OUT std_logic
		);
	END COMPONENT;

	COMPONENT top_cdr
	PORT(
		DT_IN : IN std_logic;
		SPEED_SEL : IN std_logic;
		CLK : IN std_logic;
		RST : IN std_logic;          
		DT_OUT : OUT std_logic;
		SAMPLE_EN : OUT std_logic;
		TST_CLK_OUT : OUT std_logic
		);
	END COMPONENT;
	
	COMPONENT prbschk
	PORT(
		CLK2M : IN std_logic;
		EN : IN std_logic;
		RST : IN std_logic;
		ERR_RST : IN std_logic;
		PRBSIN : IN std_logic;          
		ERR : OUT std_logic;
		RT_ERR : OUT std_logic
		);
	END COMPONENT;

--STOP COMPONENT DECLARATION 

--START SIGNAL DECLARATION
SIGNAL speed_sel, clk2m, prbs, en, dt_en, rec_clk2m : STD_LOGIC_VECTOR (1 downto 0);
SIGNAL speed_sel_cdr, dt_out, err, err_rst, dt_cdr_in : STD_LOGIC_VECTOR (1 downto 0);
SIGNAL sel_1, sel_2, clk: STD_LOGIC;
SIGNAL ctrl_0, ctrl_1: STD_LOGIC_VECTOR (12 downto 0);
SIGNAL control0       : std_logic_vector(35 downto 0);
signal async_in   : std_logic_vector(1 downto 0);
signal async_out  : std_logic_vector(63 downto 0);
signal center_f0, center_f1: std_logic_vector (31 downto 0);
SIGNAL RST 		: std_logic;
--STOP SIGNAL DECLARATION


begin

center_f0<=(x"037EB204") when speed_sel(0)='1'else (x"02A2957A");
center_f1<=(x"037EB204") when speed_sel(1)='1'else (x"02A2957A");
CKE<=rec_clk2m;
DTE(0)<=dt_out(0);
DTE(1)<=dt_out(1);

dt_cdr_in(0)<=prbs(0) when sel_1='0' else prbs(1);

dt_cdr_in(1)<=prbs(1) when sel_2='0' else prbs(0);

	ibufgds_i : IBUFGDS port map(
        	O      =>      CLK, 
        	I      =>      CLK_P,
        	IB     =>      CLK_N
    	);

	Inst_vco_1: vco PORT MAP(
		CTRL => ctrl_0,
		CENTER_F => center_f0,
		CLK => clk,
		RST => RST,
		SAMPLE_PHASE => '0',
		PHASE => open,
		PHASE_VALID => open,
		TST_MSB => clk2m(0),
		SAMPLE_90 => open,
		SAMPLE_EN => dt_en(0)
	);
	
	Inst_vco_2: vco PORT MAP(
		CTRL => ctrl_1,
		CENTER_F => center_f1,
		CLK => clk,
		RST => RST,
		SAMPLE_PHASE => '0',
		PHASE => open,
		PHASE_VALID => open,
		TST_MSB => clk2m(1),
		SAMPLE_90 => open,
		SAMPLE_EN => dt_en(1)
	);

	Inst_prbsgen_1: prbsgen PORT MAP(
		CLK => clk,
		EN => dt_en(0),
		RST => RST,
		PRBSOUT => prbs(0) 
	);

	Inst_prbsgen_2: prbsgen PORT MAP(
		CLK => clk,
		EN => dt_en(1),
		RST => RST,
		PRBSOUT => prbs(1)
	);

	Inst_top_cdr_1: top_cdr PORT MAP(
		DT_IN => dt_cdr_in(0),
		DT_OUT => dt_out(0),
		SPEED_SEL => speed_sel_cdr(0),
		CLK => clk,
		RST => RST,
		SAMPLE_EN => en(0),
		TST_CLK_OUT => rec_clk2m(0)
	);
	
	Inst_top_cdr_2: top_cdr PORT MAP(
		DT_IN => dt_cdr_in(1),
		DT_OUT => dt_out(1),
		SPEED_SEL => speed_sel_cdr(1),
		CLK => clk,
		RST => RST,
		SAMPLE_EN => en(1),
		TST_CLK_OUT => rec_clk2m(1) 
	);
	
	Inst_prbschk_1: prbschk PORT MAP(
		CLK2M => clk,
		EN => en(0),
		RST => RST,
		ERR => err(0),
		ERR_RST => err_rst(0),
		PRBSIN => dt_out(0)
	);
	
	Inst_prbschk_2: prbschk PORT MAP(
		CLK2M => clk,
		EN => en(1),
		RST => RST,
		ERR => err(1),
		ERR_RST => err_rst(1),
		PRBSIN => dt_out(1)
	);
	
	i_icon : icon
    	port map(
      		control0    => control0
    	);
    	
    	i_vio : vio
    	port map(
      		control   => control0,
      		async_in  => async_in,
      		async_out => async_out
    	);
		
		ctrl_0<=async_out(12 downto 0);
		ctrl_1<=async_out(25 downto 13);
		speed_sel<=async_out(27 downto 26);
		sel_1<=async_out(28);
		sel_2<=async_out(29);
		speed_sel_cdr<=async_out(31 downto 30);
		err_rst<=async_out(33 downto 32);
		RST<=async_out(34);
		async_in(1 downto 0)<= err;
		

end Behavioral;