freq_meter.vhd

Clock data recovery .........good example

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.0
--  \   \        Filename: freq_meter.vhd
--  /   /        Date Last Modified:  Thu Jan 17 2008
-- /___/   /\    Date Created: Wed May 2 2007
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: This is a frequency meter, only for the testbench 
--         
--         
--Revision History:
--    Rev 1.0 - First created, P. Novellini and G. Guasti, Wed May 2 2007.
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_COMPLEX.ALL;
use IEEE.MATH_REAL.ALL;
library MODELSIM_LIB;
use MODELSIM_LIB.util.ALL;



library UNISIM;
use UNISIM.VComponents.all;

entity f_meter is
    Port ( in_sig : in  STD_LOGIC;
           out_f : out  REAL);
end f_meter;

architecture Behavioral of f_meter is

begin



PROCESS (in_sig)
-- START DECLARATIONS
VARIABLE strt,stp,diff: time:=0 ps;
VARIABLE alt: BOOLEAN:=FALSE;
-- END DECLARATIONS
begin
if in_sig='1' and in_sig'event and NOT(alt) then
		strt:=NOW;
		alt:=TRUE;
elsif in_sig='1' and in_sig'event and alt then	
		stp:=NOW;
		diff:=stp-strt;
--		out_f<=1.0e12/diff;
		out_f<=1.0e6/to_real(diff)-2.0;
		alt:=FALSE;
end if;
end PROCESS;



end Behavioral;