tb_cdr.vhd

Clock data recovery .........good example

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.0
--  \   \        Filename: prbschk.vhd
--  /   /        Date Last Modified:  Thu Jan 17 2008
-- /___/   /\    Date Created: Wed May 2 2007
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: This is the test bench for the CDR 
--         
--         
--Revision History:
--    Rev 1.0 - First created, P. Novellini and G. Guasti, Wed May 2 2007.
------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_cdr_vhd IS
END tb_cdr_vhd;

ARCHITECTURE behavior OF tb_cdr_vhd IS 

	-- START DECLARATIONS
	COMPONENT top_cdr
	PORT(
		DT_IN : IN std_logic;
		SPEED_SEL : IN std_logic;
		CLK : IN std_logic;
		RST : IN std_logic;          
		DT_OUT : OUT std_logic;
		SAMPLE_EN: OUT STD_LOGIC; 
		TST_CLK_OUT : OUT std_logic
		);
	END COMPONENT;
	
	COMPONENT prbschk
	PORT(
		CLK2M : IN std_logic;
		EN : IN std_logic;
		RST : IN std_logic;
		ERR_RST : IN std_logic;
		PRBSIN : IN std_logic;          
		ERR : OUT std_logic;
		RT_ERR : OUT std_logic
		);
	END COMPONENT;
	
	COMPONENT ph_meter
   PORT( 
		in_sig_1,in_sig_2 : in  STD_LOGIC;
      out_ph1 : out  REAL);
	END COMPONENT;
	
	COMPONENT vco
	PORT(
		CTRL : IN std_logic_vector(12 downto 0);
		CENTER_F: in std_logic_vector (31 downto 0);
		CLK : IN std_logic;
		RST : IN std_logic;
		SAMPLE_PHASE : IN std_logic;          
		PHASE : OUT std_logic_vector(15 downto 0);
		PHASE_VALID : OUT std_logic;
		TST_MSB : OUT std_logic;
		SAMPLE_90 : OUT std_logic;
		SAMPLE_EN : OUT std_logic
		);
	END COMPONENT;
	
	COMPONENT prbsgen
	PORT(
		CLK : IN std_logic;
		EN: IN std_logic;
		RST : IN std_logic;          
		PRBSOUT : OUT std_logic
		);
	END COMPONENT;
	
	--Inputs
	SIGNAL SPEED_SEL :  std_logic := '0';
	SIGNAL CLK :  std_logic := '0';
	SIGNAL RST :  std_logic := '0';

	--Outputs
	SIGNAL DT_OUT :  std_logic;
	SIGNAL dt_en: std_logic;
	SIGNAL out_f, out_ph : REAL;
	SIGNAL TST_CLK_OUT :  std_logic;
	SIGNAL SAMPLE_EN :  std_logic;
	SIGNAL ctrl_0: std_logic_vector(12 downto 0);
	SIGNAL clk_drv, prbs_data: std_logic;
	SIGNAL center_f: std_logic_vector (31 downto 0);
	-- STOP DECLARATIONS

BEGIN

	center_f<=(x"037EB204") when SPEED_SEL='1'else (x"02A2957A");
	-- Instantiate the Unit Under Test (UUT)
	uut: top_cdr PORT MAP(
		DT_IN => prbs_data,
		DT_OUT => DT_OUT,
		SPEED_SEL => SPEED_SEL,
		CLK => CLK,
		RST => RST,
		SAMPLE_EN => SAMPLE_EN,
		TST_CLK_OUT => TST_CLK_OUT
	);
	
	inst_ph_meter: ph_meter PORT MAP(
		in_sig_1 => TST_CLK_OUT,
		in_sig_2 => clk_drv,
      	out_ph1 => out_ph
	);
	
	Inst_vco_1: vco PORT MAP(
		CTRL => ctrl_0,
		CENTER_F => center_f,
		CLK => CLK,
		RST => RST,
		SAMPLE_PHASE => '0',
		PHASE => open,
		PHASE_VALID => open,
		TST_MSB => clk_drv,
		SAMPLE_90 => open,
		SAMPLE_EN => dt_en 
	);
	
	Inst_prbsgen_1: prbsgen PORT MAP(
		CLK => clk,
		EN=> dt_en,
		RST => RST,
		PRBSOUT => prbs_data 
	);
	
	Inst_prbschk: prbschk PORT MAP(
		CLK2M => CLK,
		EN => SAMPLE_EN,
		RST => RST,
		ERR => open,
		ERR_RST => '0',
		RT_ERR => open,
		PRBSIN => DT_OUT
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
			ctrl_0<= "0000000000010";
		wait for 100 ns;
			ctrl_0<= "0000000000010";
			RST<='0';
			SPEED_SEL<='1';
		wait for 650 ns;
			RST<='1';
		-- Place stimulus here
			ctrl_0<= "0100000000010";
		wait for 5 ms;
			ctrl_0<= "0100000000010";
		wait for 5 ms;
			ctrl_0<= "0100000000010";
		wait for 5 ms;
			ctrl_0<= "0100000000010";
		wait for 350 ms;
			ctrl_0<= "0000000000000";



		wait; -- will wait forever
	END PROCESS;
CLK<=not(CLK) after 3.333333 ns;


END;