sys_init.c

一些linux和uboot的学习笔记

#include "AT91SAM9261.h"

#define MULA (96UL)
#define DIVA (9UL)
#define MCK  ((96+1)/9/2*18432000)

#define SDRAM_BASE    0x20000000

void uart_init();
void sdram_init();

void sys_init(void)
{
    AT91PS_PMC     pPMC = AT91C_BASE_PMC;
    int sdram_test = 0;
    int i = 0;

    //* Watchdog Disable
    //    AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;

	//* Set MCK at 48 054 850
    // 1 Enabling the Main Oscillator:
        // SCK = 1/32768 = 30.51 uSecond
    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
       pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
        // Wait the startup tim
        while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
	// 2 Checking the Main Oscillator Frequency (Optional)
	// 3 Setting PLL and divider:
		// - div by 14 Fin = 1.3165 =(18,432 / 14)
		// - Mul 72+1: Fout =	96.1097 =(3,6864 *73)
		// for 96 MHz the erroe is 0.11%
		// Field out NOT USED = 0
		// PLLCOUNT pll startup time estimate at : 0.844 ms
		// PLLCOUNT 28 = 0.000844 /(1/32768)
       pPMC->PMC_PLLAR = ( (AT91C_CKGR_DIVA & DIVA ) |
                            (AT91C_CKGR_PLLACOUNT & (28<<8)) |
                            (AT91C_CKGR_MULA & (MULA<<16))|
	                     AT91C_CKGR_SRCA|
			      AT91C_CKGR_OUTA_2);


        // Wait the startup time
        while(!(pPMC->PMC_SR & AT91C_PMC_LOCKA));
        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
 	// 4. Selection of Master Clock and Processor Clock
 	// select the PLL clock divided by 2
 	   pPMC->PMC_MCKR =  AT91C_PMC_PRES_CLK_2;
 	    while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));

	    pPMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK|AT91C_PMC_PRES_CLK_2  ;
 	    while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
        uart_init();
        UartSendst("PLL init sucsecc!!\n");
        UartSendst("UART0 init sucsecc!!\n");
        sdram_init();
	while(i-- > 0)
	{
	    asm("nop");
	}
        *(int *)(0x20000000+0x5555) = 0x55555555;
	i = 100;
	while(i-- > 0)
	{
	    asm("nop");
	}
        sdram_test =  *(int *)(0x20000000+0x5555);
        if(0x55555555 == sdram_test)
	{
	    *(int *)(0x20000000+0xaaaa) = 0xaaaaaaaa;
	     sdram_test =  *(int *)(0x20000000+0xaaaa);
            if(0xaaaaaaaa == sdram_test)
	    {
	          for(i=0; i<25 ; i++)
	          {
                      *(int *)(0x20000000+(1<<i)) = 0xaaaaaaaa;
              	      sdram_test =  *(int *)(0x20000000+(1<<i));
                      if(0xaaaaaaaa == sdram_test)
		      {
                           UartSendst("SDRAM addrbit sucsecc!!\n");
		      }
		  }
                  UartSendst("SDRAM init sucsecc!!\n");
	    }
        }
        UartSendst("BOOT LOAD RUN!!\n");
}

void uart_init()
{
   AT91C_BASE_PMC->PMC_PCER  =1 << AT91C_ID_US0;
   AT91C_BASE_PIOC -> PIO_ASR = AT91C_PC9_RXD0 | AT91C_PC8_TXD0;
   AT91C_BASE_PIOC -> PIO_BSR = 0;
   AT91C_BASE_PIOC -> PIO_PDR = AT91C_PC9_RXD0 | AT91C_PC8_TXD0;
//   AT91F_US0_CfgPIO();
   //AT91F_PDC_Close((AT91PS_PDC) &(AT91C_BASE_US0->US_RPR));
   AT91C_BASE_US0->US_MR = AT91C_US_USMODE_NORMAL  | AT91C_US_CLKS_CLOCK
                     |AT91C_US_CHMODE_NORMAL | AT91C_US_PAR_NONE
                     |AT91C_US_CHRL_8_BITS | AT91C_US_NBSTOP_1_BIT
                     ;
   AT91C_BASE_US0->US_BRGR = (unsigned int) (99328000/(115200*16)) ;

   AT91C_BASE_US0 -> US_CR = AT91C_US_RXEN;
   AT91C_BASE_US0 -> US_CR = AT91C_US_TXEN;
   AT91C_BASE_US0 -> US_CR = AT91C_US_RSTRX;
   AT91C_BASE_US0 -> US_CR = AT91C_US_RXEN;
}

void sdram_init()
{
   unsigned int open_sdram_io = 0;
   unsigned int sdram_cr = 0;
   int counter = 0;
   int read_data = 0;
   AT91C_BASE_MATRIX -> MATRIX_EBICSA = 0x1003a;
   open_sdram_io =( AT91C_PC16_D16 | AT91C_PC17_D17 | AT91C_PC18_D18
            |AT91C_PC19_D19 | AT91C_PC20_D20 | AT91C_PC21_D21
            |AT91C_PC22_D22 | AT91C_PC23_D23 | AT91C_PC24_D24
            |AT91C_PC25_D25 | AT91C_PC26_D26 | AT91C_PC27_D27
            |AT91C_PC28_D28 | AT91C_PC29_D29 | AT91C_PC30_D30 | AT91C_PC31_D31);
   AT91C_BASE_PIOC -> PIO_ASR = open_sdram_io;
   AT91C_BASE_PIOC -> PIO_BSR = 0;
   AT91C_BASE_PIOC -> PIO_PDR = open_sdram_io;
   sdram_cr =( AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2
       |AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS
       |AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | AT91C_SDRAMC_TRP_2
       |AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 );
   AT91C_BASE_SDRAMC -> SDRAMC_CR = sdram_cr;
   AT91C_BASE_SDRAMC -> SDRAMC_MDR = 0x00000000;
   for(counter=0; counter<20000; counter++)
   {
       asm("nop");
   }
   AT91C_BASE_SDRAMC -> SDRAMC_MR = AT91C_SDRAMC_MODE_NOP_CMD;
   *(int *)0x20000000 = 0xaaaaaaaa;

   AT91C_BASE_SDRAMC -> SDRAMC_MR = AT91C_SDRAMC_MODE_PRCGALL_CMD;
   *(int *)0x20000000 = 0xaaaaaaaa;
   for(counter=0; counter<10; counter++)
   {
       asm("nop");
   }
   AT91C_BASE_SDRAMC -> SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD;
   for(counter=0; counter<8; counter++)
   {
       *(int *)0x20000000 = 0xaaaaaaaa;
       asm("nop");
   }
   AT91C_BASE_SDRAMC -> SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD;
   *(int *)0x20000000 = 0XAAAAAAAA;
   AT91C_BASE_SDRAMC -> SDRAMC_MR =  AT91C_SDRAMC_MODE_NORMAL_CMD;
   *(int *)(0x20000000+0x20) = 0x55555555;
   AT91C_BASE_SDRAMC -> SDRAMC_TR = 781;


}